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- Improved network configuration by validating the port used at simulation start (C37.118 Slave, DNP3 Slave, IEC 60870-5-104 Slave, IEC 61850 MMS, MODBUS TCP Slave, OPC-UA Server)
OPAL-RT Board
- Added support for new mezzanines OP5367-1, OP5367-3 and OP5367-5
- Added capability to maintain common configuration elements when switching between bitstream configurations
- Added capability to maintain the board configuration when changing the chassis type
- Added support for the OP4512 and OP4610 chassis
- Added support for 64 ports LoadIN and LoadOUT
- Improved configuration file management for the FPGA scope feature
- Fixed various FPGA enumeration issues
C37.118 Slave
- Added support to scale asynchronous computation on multiple cores depending on the amount of PMUs, their data rate, and size
- Fixed limitation of 1000 slaves per instance
- Fixed communication issue when the IDs of consecutive PMUs are not in ascending order
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- Improved network configuration validation for MMS
- Fixed stack trace appearing at reset
Signal Generator
Added support for .oprec as input data files
Synchronization
Added support for C37.238-2017 sync profile for Oregano
Added capability to launch the synchronization setup tool at boot time, thus accelerating simulation start time after a system reboot
- Added support for Oregano card revision 2.3 (OPAL-RT Linux x64-based)
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