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Each of those ports is a signal with a UFix33_0 format. For these signals, the first 32 bits represent the data and bit 33 (most significant bit) is the valid bit, indicating when the information is updated.

• In synchronous mode (default) the valid bit is in sync with the ModelSync or model calculation step (active high for one FPGA clock duration);
• In asynchronous or in burst mode, the valid bit is active on arrival of the data.

Those ports are shown on the block when the parameter Provide Start Of Frame enables it. The corresponding port provides a pulse signal of one FPGA clock duration.

The provided signal allows the user to easily unpack the data when multiple data are being received per calculation step through the same port, which is the case when Transfer mode is set to asynchronous for the specified port.