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Location
This example model can be found in the software under the category "Renewable Energy" with the file name "FPGA-BASED_Dual_Active_Bridge.ecf".
Description
This project demonstrate the use of the Gen5 eHSx128 solver to compute the outputs of a FPGA-based Dual Active Bridge circuit in real time, that run on a Versal board. The FPGA-based circuit is a bidirectional DC-DC converter with two bridges separated by a Single phase idela two winding transformer. This circuit is created isung the OPAL-RT Schematic Editor. With this example project, the user is able to control the simulation parameters in real-time via HYPERSIM.
Requirements
The HYPERSIM, Schematic Editor/Unified Database, and eFPGASIM toolboxes must be installed on the host and target computers to run this example model properly. Please refer to the product documentation for details on version compatibility. Also, the minimal time step on a CPU core is 10µs.
Configuration and Interface
The plant model (Dual_Active_Bridge_OP48XX) built in the schematic editor is configured to read the PWM pulses from the Digital In card of OPAL-RT’s real-time simulator. If you are using this model on board that doesn’t have bi-directional I/Os, you will need to set a digital loopback wire on the simulator between the Digital Inputs and Digital Outputs channels 0 to 15.
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To configure PWM outputs, the modulation signals, the carrier wave frequencies and the dead-time need to be routed to the duty and frequency of the PWM output.
IO Configuration
Since part of the simulation is done through eHS, it is required to connect HYPERSIM to it. Here are the steps for that configuration:
Open the I/O Interface Configuration
Add an OPAL-RT Board
Select the correct Chassis ID and write the IP address. This example uses an OP4815 (Versal) target.
Select Optical for the type of generated synchronization signal.
Select Standard repositories for the bitstream configuration location, then select your bitstream configuration file. In this example, the bitstream configuration file is
OP5145_2-EX-0001-eHSx128_Gen5_Machines_IOConfig1.opal
And the bitstream name is
OP5145_2-EX-0001-3_5_0_817-eHSx128_Gen5_500Mhz_Machines_IoConf1-5A-23.pdi
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Simulation and Results
With this model you can obtain two results by switching the control mode. If the Control mode is set to “Open Loop” which is 1 in the constant block in HYPERSIM, the V_out does not converge to the V_Ref :
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