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Bitstream Configuration
Every bitstream file (.bin), or programmable definition file Versal boot Programmable Device Image (.pdi), programmed into an FPGA interfaced with the OPAL-RT Board driver must have an associated configuration file. The driver requires a description of the hardware installed in the simulator to correctly interface with it.
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The following options can be configured through the General section:
| Chassis type | Select the chassis used in the simulation. |
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| IP address | In order to allow bitstream programming, this field will be available for the user to enter the appropriate IP address that is displayed on the Chassis LCD. NOTE: Only visible when Chassis type is OP4810 or OP4815. |
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| Chassis name | This field will be available for the user to configure a custom name to be displayed on the Chassis LCD. NOTE: Only visible when Chassis type is OP4810 or OP4815. |
| Chassis ID | Enter the chassis ID of the selected FPGA board in the simulation. |
| Use external synchronization source | When selected, the board uses an external synchronization source as opposed to its internal clock. | |||||
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| Type of generated synchronization signal | If the Use external synchronization source box above is unchecked, then this parameter is visible, allowing the user to choose the medium where the FPGA outputs its synchronization pulse: choices are through the optical cable or through the audio cable. NOTE: Spartan-3 cards (OP5142) have only one type of synchronization signal, RTSI. This signal is routed to the necessary synchronization converters (audio or optical), according to the system's assembly. | |||||
| Operate as a hardware synchronization source | Only visible if the Use external synchronization source checkbox above is enabled. | |||||
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| Type of expected synchronization signal | This parameter is only visible if the Use external synchronization source checkbox above is enabled. It is a drop-down menu giving the user the choice to synchronize either through copper or optical cables. NOTE: Spartan-3 cards (OP5142) have only one type of synchronization signal, RTSI. This signal is routed to the necessary synchronization converters (audio or optical), according to the system's assembly. | |||||
| Bitstream configuration location | This field allows either searching the bitstream configuration file using the file system or selecting it from a drop-down list based on the available files in the standard OPAL-RT repositories. | |||||
| Bitstream configuration file | If the bitstream configuration location is set to File system:
Once a file is selected and the interface has checked validity, the Folders section of the configuration panel updates to show the I/O capability of each slot as described in the file. |
| Show advanced configuration | When selected, the user can configure advanced features: | |
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| Time step factor | Denotes a multiplier for the board's speed in relation to the model's timestep. | |
| Enable FPGA register logger | For advanced debugging purposes, the driver will start a tool that will log all the FPGA register accesses during the initialization and the reset of the model. The logs will be saved in files named with the prefix "register_trace*". Those files are retrieved on the host PC after the reset of the model. | |
| Automatic bitstream reprogramming | If selected, bitstream programming is triggered automatically at the model load. The bitstreams should be placed at the model path and must have the name given in the configuration file used. If the bitstream currently programmed in the board is found to be the same as the one about to be programmed, then the bitstream is reloaded into the FPGA. The field is not available if the bitstream file is not Found. | |
| Bitstream file name | A static field showing the bitstream found based on the selected bitstream configuration file. | |
| Force | This option flashes the board even if it is already programmed with the same bitstream. | |
| Disable strict hardware mismatch validation | If selected, the | |
This field will be available for the user to configure a custom name to be displayed on the Chassis LCD.
NOTE: Only visible when Chassis type is OP4810 or OP4815.
In order to allow bitstream programming, this field will be available for the user to enter the appropriate IP address that is displayed on the Chassis LCD.
NOTE: Only visible when Chassis type is OP4810 or OP4815| use of multiple I/O card types based on general compatibility rules is activated instead of exact hardware ID values. | ||
| Enable FPGA Scope | If selected, the FPGA Scope will be available when the model is executed. The option is visible only if the feature is available in the selected bitstream configuration file. | |
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| Enable virtual mode | In virtual mode, the model can be executed even if this I/O interface is not compatible with the hardware configuration of the system. The connections between the model and the I/O interface will be done during the initialization, but the I/O interface will not do anything. The virtual mode can be used to troubleshoot problems on a system without having the required hardware, or to prepare a model with different I/O interfaces even if the final hardware platform is not available. | |
For more information, contact OPAL-RT's Support team.
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When clicking this section, the fields provide the following information to the user:
| Description | Electrical characteristics of the slot. |
|---|---|
| Functionality | Type and direction of the I/Os in the slot. |
| I/O card type | I/O board identifier. |
Other parameters may appear here, depending on the I/O board type.
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- This driver must be run in Hardware Synchronized mode.
- Only XHP mode is supported.
- The disable strict hardware mismatch validation feature is not available on OP5142.
- Each FPGA must have connections with at least one subsystem running at the model's timestep (in the context of multi-rate subsystems).
- A configuration having multi-rate subsystems associated with a slave FPGA board does not support the action of Pause/Execute during the simulation.
- On all chassis, the motor models are not supported for the moment.
- Chassis type OP5143 standalone is supported only for MuSE as central with four remotes. Using it as MuSE remote is not supported . It does not support any I/Os.
- For the chassis types OP4810 and OP4815, the maximum support PDI file size is 64 MiB.
List of Compatibilities
| Chassis and FPGA board | Supported |
|---|---|
| OP4500 with an MMPK7 module | No longer supported. |
| OP4510 with a TE0741 module | Yes |
| OP4512 with a TE0741 module | |
| OP4520 I/O expansion box with a TE0741 module | |
| OP4610 with a TE0741 module | |
| OP5600 with an OP5142 board | |
| OP5600 with an OP5143 board | |
| OP5600 with an ML605 board | No |
| OP5607 I/O expansion box with a VC707 board | Yes |
| OP5707 with a VC707 board | |
| OP7020 I/O expansion box with a VC707 board | |
| OP7160/OP7161 | No |
| OP7170 | Yes |
| OP5143 standalone PCIe card | Yes |
| OP4810 | Yes |
| OP4815 | Yes |
Limitations of the Multi-System Expansion link feature
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| Chassis and FPGA board | Central | Remote |
|---|---|---|
| OP4500 with an MMPK7 module | No | No |
| OP4510 with a TE0741 module | Yes | Yes |
| OP4512 with a TE0741 module | Yes | |
| OP4520 I/O expansion box with a TE0741 module | Yes, if connected via PCIe to a simulator | |
| OP4610 with a TE0741 module | Yes | |
| OP5600 with an OP5142 board | No | No |
| OP5650 with an OP5143 board | Yes | Yes |
| OP5600 with an ML605 board | No | No |
| OP5607 I/O expansion box with a VC707 board | Yes, if connected via PCIe to a simulator | Yes |
| OP5700 with a VC707 board | Yes | |
| OP7020 I/O expansion box with a VC707 board | Yes, if connected via PCIe to a simulator | |
| OP7160/OP7161 | No | No |
| OP7170 | Yes | Yes |
| OP5143 standalone | Yes | No |
| OP4810 | No | No |
| OP4815 | No | No |