The FPGA-based Power Electronics Toolbox has, in its heart, an electric Hardware Solver (eHS).
The eHS solver is an FPGA-based technology developed by OPAL-RT for real-time power electronics simulation. Thanks to a convenient circuit schematic graphical user interface, the FPGA code is automatically generated, making FPGA-based simulation accessible to a large number of users.
The OPAL-RT electric Hardware Solver (eHS) is a powerful floating-point solver developed by OPAL-RT that enables users to simulate an electric circuit on an FPGA automatically, without having to write the mathematical equations. It combines the simplicity of building electric circuit models using either our OPAL-RT Schematic Editor or the Simscape Electrical Specialized Power Systems (SPS) Toolbox, PSIM, the PLECS Blockset, or NI Multisim software with the strength of OPAL-RT FPGA-based simulators to solve the currents and voltages within the circuit in real-time, with a sample time below 1μs.
The new 5th generation is based on state space method that allows higher order of discretization and offers better performances than the previous generation. It is currently in a beta version and is being actively developed to become our newest official generation.
The 4th generation of eHS solver uses the modified nodal analysis. It solves a conductance matrix to find the voltage at each node of the circuit, and the current in each branch. The conductance matrix of the circuit is made independent of the switch control signals through the implementation of the Pejovic1 method representing the switch impedance. With this method, a conducting switch is represented as an inductance and an open switch is represented as a capacitance so the conductance matrix does not change during the simulation.
The upcoming 5th generation is based on state space method that allows higher order of discretization and offers better performances than the previous generation. It is currently in a beta version and is being actively developed to become our newest official generation.
KEY FEATURES
1.1 CONFIGURABILITY
KEY FEATURES
1.1 CONFIGURABILITY
5th Generation
This new generation is using a new circuit analysis method based on State Space equations resolution for faster and more accurate discretization method. Switching components are now computed with enhanced fidelity thanks to the Time Stamped Bridge technology, which considers the switching events with an accuracy down to 625ps of resolution.
This generation allows the accurate simulation of frequency and/or phase -controlled power electronics systems, such as resonant converter (CLLC, LLC topologies) and Dual Active Bridge with switching frequency above 200 kHz.
4th Generation
The conductance matrix does not need to be re-computed since switches are represented using the Pejovic* method. All the matrices needed for solving the system are loaded onto the FPGA engine when the simulation is initiated. Reconfiguring the engine with specific firmware for each application is not necessary. This feature makes running real-time simulations of electrical systems at high sampling rates as easy as any RT-LAB simulation.
* P. Pejovic and D. Maksimovic, "A new algorithm for simulation of power electronic systems using piecewise-linear device models," in IEEE Transactions on Power Electronics, vol. 10, no. 3, pp. 340-348, May 1995, doi: 10.1109/63.388000.
5th Generation
This new generation is using a new circuit analysis method based on State Space equations resolution for faster and more accurate discretization method. Switching components are now computed with enhanced fidelity thanks to the Time Stamped Bridge technology, which considers the switching events with an accuracy down to 625ps of resolution.
This generation allows the accurate simulation of frequency and/or phase -controlled power electronics systems, such as resonant converter (CLLC, LLC topologies) and Dual Active Bridge with switching frequency above 200 kHz.
1.2 PERFORMANCE
4th 5th Generation : The sample time of the electrical system solved by the eHS solver ranges from 200ns 90ns to 4μs, depending on the circuit complexity.
5th 4th Generation : The sample time of the electrical system solved by the eHS solver ranges from 90ns 200ns to 4μs, depending on the circuit complexity.
1.3 COMPATIBILITY
eHS solvers provide a flexible environment that allows the user to design the simulated circuit in various netlist editors such as
OPAL-RT Schematic Editor
SPS and PLECS Simulink toolboxes
Powersim PSIM
NI Multisim Veristand software
1.4 SCALABILITY
eHS exists in various licence license classes to accommodate low to high-end FPGA-based platforms. It is capable of simulating a Boost circuit with time step as low as 200ns (4th Generation) and 90ns (5th generation), as well as a micro-grid system with outstanding resolution. Depending on the use case, it is possible to interconnect several eHS cores using a multi-FPGA system with low latency SFP 5Gbps links between chassis.
1.5 PARAMETER SETS
It is possible to modify the component values during simulation to apply load variations and faults using the parameter set feature.
Choose your best parameter set flow based on your requirements
Performance - Option From FPGA: Switch from one set of parameters to another in a single time step.
Limitation: Number of parameter sets available depends on the size of FPGA and the circuit simulated on the FPGA.Flexibility - Option From CPU: Unlimited number of parameters sets
Limitation: Switching from one set of parameters to another will be done within a second.
SPECIFICATIONS
(See Supported features for more details)
2.1 EHS
GEN4The circuit is designed using blocks in supported netlist editors. A limited number of elements, chosen from a specific list, can be included in each circuit. The maximum number of circuits that can be simulated in one real-time model depends on the firmware installed onto the solver hardware and the number of available eHS licenses installed onto the simulation system. The 4th Generation of eHS comes in various sizes to respond to different needs in terms of FPGA size, simulation complexity, and compatibility. Table 1 describes the existing eHS gen4 cores followed by their associated specifications: Features eHSx16 eHSx32 eHSx64 eHSx128
LicenceLicense class | ||||
|---|---|---|---|---|
Features | x128 | x64 | x32 | x16 |
Targeted platforms
OP4512 (Kintex7 410T)
OP4610 (IO/XG) (Kintex7 410T)
OP5607 - OP5700 - OP5707 (IO/XG) (Virtex7-485T)
OP4510 (Kintex7 325T)
OP4512 (Kintex7 410T)
OP4610 (IO/XG) (Kintex7 410T)
OP5607 - OP5700 - OP5707 (IO/XG) (Virtex7-485T)
OP4512 (Kintex7 410T)
OP4512 (Kintex7 410T)
Number of inputs | 128 | 64 | 32 | 16 |
Number of |
outputs1 | 128 | 64 | 32 | 16 |
Number of low latency outputs1
128
64
32
16
Number of switches
144
72
48
Total number of switches6 | 144 | 72 | 48 | 12 |
Number of Non-Linear/Variable components | 64 | 32 | 16 | 8 |
LCA capability2 | Yes | |||
Maximum number of states3 | ||||
344
168
344 | ||||
Number of resistors | Unlimited | |||
Switches type supported | IGBT/Diode, Diode, Breaker, Thyristor, Ideal Switch, FET, Cyclo Converter, 2-Lvl Half- Bridge, 3 | |||
Lvl NPC, 3Lvl T-type | ||||
Non-switching devices supported | Resistor, Inductor, Capacitor, Ideal Transformer, Mutual inductance, Serial and Parallel RLC, PI Line, Surge arrester, Variable Serial RL and Parallel RC, Saturable Inductor | |||
Calculation power | ||||
102. |
4 GFLOPS |
25.6 GFLOPS
12.8 GFLOPS
limited by time step | limited by time step | limited by time step | ||
Maximum number of parameter sets | From FPGA: Up to 512 scenarios4 From CPU: Unlimited5 | |||
Compatible circuit editors | OPAL-RT Schematic Editor | |||
, Powersim PSIM(import), NI Multisim software(import) |
1 See details about License and components
2 LCA stands for Loss Compensation Algorithm. This feature optimizes losses for standard topologies such as the two-level and the three-level NPC arm converters.
3 Estimated values. The maximum number of states depends on the number of inputs and outputs that needs to be computed as well. There is no hard coded limit. If the time step required exceeds the solver’s limit (4.8us), a compilation error will occur due to overpassing the circuit size limit.
4 The number of scenario on FPGA available for a given circuit depends on the circuit complexity. Scenarios are not supported on the OP4200 target.
5 The number of scenario on CPU available only depends on your memory allocated to Matlab.
2.1 eHS - Advanced Performance Add-on (GEN5)
License class
Features
x128
x64
x32
x16
Targeted platforms
OP4512 (Kintex7 410T)
OP4610 (IO/XG) (Kintex7 410T)
OP5607 - OP5700 - OP5707 (IO/XG) (Virtex7-485T)
OP4815 - OP4810 (Versal)
Number of inputs
128
64
32
16
Number of high latency outputs1
128
64
32
16
Number of low latency outputs1
128
64
32
16
Number of switches
128
72
48
12
Number of Non-Linear/Variable components
64
32
16
8
LCA capability2
Yes
Maximum number of states3
344
344
344
344
Number of resistors
Unlimited
Switches type supported
IGBT/Diode, Diode, Breaker, Thyristor, Ideal Switch, FET, Cyclo Converter, 2-Lvl Half- Bridge
Non-switching devices supported
Resistor, Inductor, Capacitor, Ideal Transformer, Mutual inductance, Serial and Parallel RLC, PI Line, Surge arrester, Variable Serial RL and Parallel RC, Saturable Inductor
Calculation power
102.4 GFLOPS
limited by time step
limited by time step
limited by time step
Maximum number of parameter sets
From FPGA: Up to 512 scenarios4
From CPU: Unlimited5
Compatible circuit editors
OPAL-RT Schematic Editor
1 Low latency outputs are calculated as fast as possible in the solver to come up with the minimum achievable time step. On the other hand, high latency outputs are used for components not impacting the minimum time step. See details about Licence and components
2 LCA stands for Loss Compensation Algorithm. This feature optimizes losses for standard topologies such as the two-level and the three-level NPC arm converters.
3 Estimated values. The maximum number of states depends on the number of inputs and outputs that needs to be computed as well. There is no hard coded limit. If the time step required exceeds the solver’s limit (4.8us), a compilation error will occur due to overpassing the circuit size limit.
4 The number of scenario on FPGA available for a given circuit depends on the circuit complexity.
5 The number of scenario on CPU available only depends on your memory allocated to MATLAB.
MATLAB.
6 Hardware limits the maximum number of single switches to 128 and the number of 2-lvl Half-bridges to 64
2.2 EHS High Performances
eHS comes with a performance license enabling multiple features:
Our new generation of solver allows up to 90ns minimum time step.
Our new generation of solver supports de-coupling blocks in the same large circuit to be able to reduce efficiently the minimum time step of large circuit by placing in a strategic manner specific de-coupling blocks between subcircuits. (more details and examples)
3 INTENDED AUDIENCE AND REQUIRED SKILLS AND KNOWLEDGE
The intended user of the eHS solver within OPAL-RT’s eFPGAsim eFPGASIM Toolbox is an R&D, algorithm, or Test Engineer requiring an easily reconfigurable, very-high-speed electrical circuit solver that does not require knowledge of time-consuming custom firmware development and configuration processes.
4 EXTERNAL TOOLS
4.1 OPAL-RT SCHEMATIC EDITOR
OPAL-RT Schematic Editor is brand new circuit editor allowing user to design in a highly efficient user interface the circuit that will be used by eHS. Schematic Editor is compatible with RT-LAB and HYPERSIM to provide you with a clear and simplified eHS experience.
4.2 SIMULINK
Simulink is a software package developed by The MathWorks, Inc. that enables modeling, simulation and analysis of dynamic systems. Models are described graphically, following a precise format based on a library of blocks. The eHS solver uses Simulink to define models that will be executed during an RT-LAB simulation. Users are expected to have a clear understanding of Simulink operation, particularly regarding model definition and simulation parameters.
4.3 SIMSCAPE ELECTRICAL SPECIALIZED POWER SYSTEMS (SPS) AND PLECS SIMULINK TOOLBOXES
The SPS and PLECS Blockset toolboxes provide libraries and analysis tools useful for modeling and simulating electrical systems. They are used by the eHS only as circuit description environments. They can be used from within the RT-LAB environment for real-time simulation, but fail to achieve the very high sample rate that can be attained with the eHS solver. It can be useful, though, to use these simulation tools to compare the results to those of the eHS solver.
4.4 PSIM
PSIM, developed by Powersim, is an Electronic circuit simulation software package, designed specifically for use in power electronics and motor drive simulations but can be used to simulate any electronic circuit. It is used by the eHS only as circuit description environments, and its netlist file can be used from within the RT-LAB environment for real-time simulation, but fails to achieve the very high sample rate that can be attained with the eHS solver. It can be useful, though, to use these simulation tools to compare the results to those of the eHS solver.