Versions Compared

Old Version 3

changes.mady.by.user Sylvain Ménard

Saved on

compared with

New Version Current

changes.mady.by.user Etienne Leduc

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.


Model name

3-phase 2-level voltage source inverter with RL load

Model diagram

Inputs (sources)

14

Switches

6

Outputs (measurements)

68

States (L, C, ...)

35

Hardware

OP5707XG

  • Motherboard: X11DPL-i
    • Processor: Intel(R) Xeon(R) Gold 5222 CPU @ 3.80GHz; 8 cores

    OP4810-IO

    • FPGA: Xilinx Virtex™ 7RAM: 32 GB Versal VM1302

    Software

    • Platform: RT-LAB or HYPERSIM

    Minimum license required

    		eHSx32eHSx16

    Minimum time-step

    eHS Gen4eHSx16 Standard: 250 230 ns

    eHS Gen5: coming soon!High Performance: 100 ns