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Introduction
The FPGA Scope enables the monitoring of high-speed signals internal to an FPGA board connected to an OPAL-RT Simulator, acquired directly on FPGA at a rate faster than the simulation step. The feature relates to the low-level acquisition system, and when the feature is enabled, data is made available to the user for visualization through the ScopeView interface or through the DataLogger APIs.
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The feature is available in all OPAL-RT firmware provided as an OPBIN file, for FPGA cards connected to the simulation through a PCI-express interface. It is enabled through the option “Enable FPGA Scope” in the OPAL-RT Board I/O configuration.
Typically, all simulator input/output signals are available for visualization through the FPGA Scope. Additionally, if present, FPGA-based controllers and solvers such as eHS, or custom probes on other functionalities, can provide signals to the FPGA Scope.
OPAL-RT Board
The feature is enabled through the option “Enable FPGA Scope” in the OPAL-RT Board I/O configuration.
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S-Function IOs
The FPGA Scope is enabled through the option “Enable FPGA Scope” in the OpCtrl Block.
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Visualizing the signals
ScopeView
From the time the simulation is executed, the signals acquired by the FPGA Scope can be visualized in ScopeView following this procedure:
From RT-LAB, open ScopeView.
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In ScopeView, load the Data Source by selecting the simulator IP address into the "Target" field of the FPGA Scope tab, then click the refresh button. Once selected, press "Load".
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In the signal selection interface, select the signals to be visualized from the list of signals
In the ScopeView oscilloscope interface, the trigger signal selection is displayed. Adjust acquisition period and window size, trigger characteristics and then run an acquisition by clicking the black "Start" button.
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Example Model
The procedure above is illustrated in an example model for an OP4510 simulator. To try the example model, create a new project based on template Features > FPGAScope.
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Additional information
Acquisition period
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