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changes.mady.by.user Sylvain Ménard

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changes.mady.by.user Etienne Leduc

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Model name

Back3-phase 2-level back-to-back converter

Model diagram

Inputs (sources)

36

Switches

1512

Outputs (measurements)

96

States (L, C, ...)

67

Hardware

OP5707XG

  • Motherboard: X11DPL-i
  • Processor: Intel(R) Xeon(R) Gold 5222 CPU @ 3.80GHz; 8 cores
  • FPGA: Xilinx Virtex™ 7
    • RAM: 32 GB

    OP4810-IO

    • FPGA: Xilinx Versal VM1302

    Software

    • Platform: RT-LAB or HYPERSIM

    Minimum license required

    		eHSx32eHSx16

    Minimum time-step

    		eHS Gen4

    eHSx16 Standard:

    270

    300 ns

    eHS

    Gen5: coming soon!

    High Performance: 95 ns