Block

Mask

Description

This block represents the output data link from the FPGA through the PCIe bus. Data may be going to the target PC (RT-LAB CPU model) or to another FPGA board in multiple chip design (only RT-LAB CPU models are supported in this version).

A maximum of 64 output ports is provided to the user for data samples and control signal transfers. One of the functions of this block is to do data conversion from the Xilinx System Generator UFix or Fix format to the uint32 data format.

This block is linked to the output ports of the OpCtrl ReconfigurableIO block found in the RT-LAB CPU model: port #1 of the OpCtrlReconfigurableIO block corresponds to DataOUT1, port #2 to DataOUT2, etc.

Two modes are available. When in FIFO mode, all data sent to the DataOUT block between two data acquisition synchronization signal pulses is transmitted. When in Register mode, the last data before the synchronization signal pulse is transmitted.

Note: Data arriving synchronously with the synchronization signal belongs to the ending timestep.

Parameters

Number of ports

Allows the user to use multiple data ports to communicate information with parallel processors. When the number of ports is changed, the length of the “Transfer Mode” string is updated accordingly.

Buffering type

Allows a user to choose whether to buffer the information in a single register where only one data sample can be transferred per calculation step or in a FIFO buffer-based mode where up to 254 samples can be transferred per calculation step. For example, a value of 010000000000101 in this field sets a FIFO on DataOUT ports 1 and 3 and 15 (MSB to LSB port representation).

In FIFO mode, the number of samples stored is determined by the number of 10 ns pulses (one FPGA clock cycle) on bit 32 (MSB) of the port in FIFO mode per calculation step.

Provide external data synchronization signal

Used to postpone the data acquisition by the DataOUT communication module.

When in normal mode, the data acquisition occurs synchronously with the synchronization signal. By using the postponed mode, users can delay the acquisition of the data from 0 to 15 clock cycles. This feature may be used to complete pipelined computation on data that belongs to the ending timestep, or to transfer serially multi-channel data acquired synchronously with the synchronization signal.

A 1 for a channel adds an input port for the developer to provide the external synchronization signal. A 0 forces the use of the ModelSync signal to be used as the data acquisition synchronization signal (default).

Inputs

Data_OUT{1,...,64}

Each of these ports is in the UFix33_0 format where the first 32 bits represent the data and bit 33 (the most significant bit) is the valid signal indicating when the data is ready.

Bit 33 can be seen as a write signal to the buffer, whether it be a register or a FIFO, in the DataOUT block. Each of those buffers is emptied and transferred to the CPU model at the beginning of each calculation step.

DataSync{1,...,64}

If requested from the block parameter panel, each of these ports enables the developer to provide an external, delayed data acquisition synchronization signal for each output data channel.

It is recommended to connect this input to a delayed version of the ModelSync signal (accessed through a “From” built-in Simulink block). The external synchronization pulse must occur within a delay of 0 to 15 clock cycles after the master ModelSync pulse. Pulses observed outside this time range will be taken into account for data transmission in the next computation step.

Outputs

DataOUT	This is a vector of signals in the uint32 format (with a length equal to the number of ports). Each one of these signals represents an output port on the OpCtrlReconfigurableIO block in the RT-LAB CPU model. This port is used for offline simulation only.

Characteristics and Limitations

This block has no special characteristics.

Direct Feedthrough	N/A
Discrete sample time	N/A
XHP support	N/A
Work offline	YES (No for ports set in FIFO mode)

DataOut