An RT-XSG model can be accessed with application-specific RT-LAB blocks from the OPAL-RT I/O library.
These blocks perform all the required data scaling and packaging to control the different analog and digital interface blocks in the RT-XSG model. The CONF file is a text-based file giving the I/O type, count and location related to each DataIn and DataOut port accessed by the RT-LAB blocks (the figure below presents a sample file). The CONF file must be supplied to the RT-LAB model along with the FPGA configuration file (BIN file), with the same file name except for the extension.
When is a CONF File Required?
The CONF file is required only if the developer wants to access the signals using the application-specific blocks from the OPAL-RT I/O library. It is not required if the signals are interfaced through the lower-level DataIN Send and DataOUT Recv blocks, for which data scaling and packaging are designed manually by the developer.
Supported Reconfigurable Hardware
The use of application-specific OPAL-RT I/O blocks through a CONF file is compatible with all FPGAs supported by RT-XSG.
Analog and Digital Signal Types Supported in the CONF File
The signal types described below can be referenced by the CONF file so that the OPAL-RT I/O blocks are able to scale and package the communication signals correctly. It is also possible to design custom I/O blocks that would use additional custom reserved signal names referenced by the CONF file.
CONF File supported signal types
| I/O type | Direction | Reserved name | Description |
|---|---|---|---|
| AnalogIn | Input | AI | Standard static analog input, inside the range [-16V, 16V], one value per channel per time step |
AnalogOut | Output | AO | Standard static analog output, inside the range [-16V, 16V], one value per channel, per time step |
| DigitalIn | Input | DI | Standard static digital input (0 or 1). One value per channel, per time step |
| Digital Out | Output | DO | Standard static digital output (0 or 1). One value per channel, per time step |
| EventDetector | Input | TSDI | A vector of states and times, giving precise information on all events that occurred on each channel during the last time step (in the RT-Events format) |
| Event Generator | Output | TSDO | A vector of states and times, giving precise information on all events that are requested on each channel during the next time step (in the RTEvents format) |
| PMW In | Input | PWMI | Duty and Frequency are retrieved from the Pulse Width Modulated signals connected to the digital input during the last time step |
| PMW Out | Output | PWMO | Pulse Width modulated signals produced using the carrier frequency and the duty cycle during the next time step |
| EncoderIn | Input | QEI | Angle and speed (frequency) of a quadrature encoded digital input triplet (A,B, Z) |
| EncoderOut | Output | QEO | Requested speed (frequency) of a quadrature encoded digital output triplet (A, B,Z) |
| Resolver In | Input | RI | Basic resolver, two poles, retrieve angle and speed from the resolved signal |
| Resolver Out | Output | RO | Single-Ended or Differential resolver signals |
| TSB In | Input | TOM | Time-stamped bridge input signal, giving equivalent RT-Events signals used by the TSB block |
| DataIn Send/DataOut Recv | Input/output | Any other name | Any other type name is permitted but can only be used with the low-level DataIN send or DataOut Recv blocks |
| LoadIn/LoadOut | Input/output | Any other name | To send or receive raw data to/from the FPGA at a specific time when enable signal is sent |
Groups, Sections, and Subsections
In order to facilitate identification, I/O lines of OPAL-RT TECHNOLOGIES hardware are organized in groups, sections, and subsections.
A group (also named slot on some platforms) corresponds to a specific position of digital or analog hardware interface inside the OPAL-RT TECHNOLOGIES chassis. Each group consists typically of two I/O mezzanine cards, sometimes referred to as sections, and labeled A and B. Each section is broken down into subsections of eight channels each.
The number of available groups depends on the chassis type, and the number of subsections composing each section of the group depends on the hardware that is installed in the section. A 32-channel interface card will be referred to as 4 subsections of eight channels.
As a standard, one RT-LAB interface block from the OPAL-RT I/O Blockset targets one subsection of hardware, and each block is associated with one DataIn or DataOut port in the RT-XSG model.
The different subsections referenced by a CONF file can be accessed independently from any number of subsystems of the real-time model, provided that each subsystem contains the corresponding OpCtrl or OpLnk block (refer to the help of these blocks for more information). However, each DataIn or DataOut port can be used only by one block in the RT-LAB design.
Note: Each line of the CONF file corresponds to one DataIN or DataOUT port number, and manages the signals of only one signal subsection. In the case of FPGA configurations that implement multiplexing of more signal types on the same subsections, more than one DataIN channel can provide packaged data that relates to the same subsection, the signal type selection being managed by a dedicated port from the DataIn or LoadIn block.
Manual CONF File Creation
The following template can be used, adding one row per DataIn and DataOut channel, as required. It is not mandatory to include all ports in the CONF file: only the ports that will be used by application-specific blocks from the OPAL-RT I/O library are required.
| Description | Slot | Section | Subsection | Count | Size | |
|---|---|---|---|---|---|---|
| DataIn1 | AO | 1 | A | 1 | 8 | 16 |
| DataIn2 | DO | 2 | A | 1 | 8 | 1 |
| DataIn3 | TSDO | 2 | A | 2 | -1 | 32 |
| DataIn4 | PWMO | 2 | A | 3 | 8 | 64 |
| (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) |
| DataOut1 | DI | 2 | B | 1 | 8 | 1 |
| DataOut2 | TSDI | 2 | B | 2 | -1 | 32 |
| (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) |
| (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) | (. . . ) |
Column Description
- PortName: The port number from either the DataIn or DataOut block;
- Description: Signal type (either one of the reserved names or any other name if the signal is to be used with the DataIn Send or DataOut Recv block);
- Slot: Location of the I/O interface hardware in the chassis;
- Section: Section of the I/O interface hardware (A or B);
- Subsection: 8-channel signal subsection of the corresponding slot/section pair;
- Count: Number of items to send per time step. A value of -1 is written for signal types for which the data count is not known a priori in RT-XSG (e.g. TSDI and TSDO signal types, as the number of events per time step, is set in the OPAL-RT I/O block itself);
- Size: Size in bits of each item to be sent. If Size < 17 bits and Count > 1, many items are concatenated into 32-bit packets for optimal communication between the RT-LAB and RT-XSG models.
Typical count and size for the OPAL-RT I/O blocks
The typical data word count and size of the different OPAL-RT I/O blocks are indicated in the table below
Signal reserved name | Typical Count | Typical Size | Description |
|---|---|---|---|
| AI | 8 | 16 | 8 analog channels, each with one 16-bit data to receive per time step. |
| AO | 8 | 16 | 8 analog channels, each with one 16-bit data to send per time step. |
| DI | 8 | 1 | 8 digital channels, each with one 1-bit data to receive per time step |
| DO | 8 | 1 | 8 digital channels, each with one 1-bit data to send per time step |
| TSDI | -1 | 32 | 32-bit time-stamped values of 8 digital channels' status. The number of values is defined in the real-time simulation model definition (Simulink block or OPAL-RT Board GUI) |
| TSDO | -1 | 32 | 32-bit time-stamped values of 8 digital channels' status. The number of values is defined in the real-time simulation model definition (Simulink block or OPAL-RT Board GUI) |
| PWMI | 8 | 64 | 8 digital channels, each with one 64-bit data to receive per time step |
| PWMO | 8 | 64 | 8 digital channels, each with one 64-bit data to receive per time step |
| QEI | 2 | 16 | The signal exchanged between RT-XSG and RT-LAB is the angle and rate values, expressed in a16-bit data. Six (6) digital channels are used in the subsection (two A, B, Z triplets) |
| QEO | 2 | 16 | The signal exchanged between RT-LAB and RT-XSG is the frequency values and other parameters, expressed in 16-bit data. Six (6) digital channels are used in the subsection (two A, B, Z triplets) |
| RI | 2 | 96 | Angle and speed is retrieved in 96-bit data, 3 analog input channels are used to receive the external carrier, sine, and cosine and 1 analog out channel might be used to output the carrier |
| RO | 2 | 160 | Parameters to generate the resolver signal are expressed in 160bit data, 1 analog input channel might be used to receive the external carrier and 3 analog-out channels for carrier, sine, and cosine |
| TOM | 8 | 16 | 8 digital channels, each with one 16-bit data to receive per time step |
OPAL-RT I/O blocks that require LoadIn
For some of the IO blocks, a LoadIn block is required and it must be specified in the conf file.
| Signal reserved name | Typical Count | Typical Size |
|---|---|---|
| PWMO | 8 | 64 |
| QEI | 2 | 32 |
| QEO | 2 | 32 |
| RI | 2 | 256 |
| RO | 2 | 32 |