Block
Mask
Description
This block generates a synchronization pulse train with the specified period. The width of the pulse equals the FPGA board clock period, during which its output value is the unsigned integer '1'. Otherwise it is the unsigned integer '0'.
Parameters
| Pulse Train Period (seconds) | The period of the pulse train, in seconds. |
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| Number of sync phases | This number defines the number of Sync output. Each Sync output has a one-step delay from the previous one. Accepted values: 1-16 |
| Add a synchronous reset port | This option provides an input port used to reset the pulse train,s internal counter's value. |
| Add the step size output port | This option provides an output port corresponding to the actual step size. |
Inputs
| Rst | If the corresponding option is activated, then an input port will be available for a reset signal. |
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Outputs
| Sync# | There will as many Sync-port as required, within the limits, corresponding to the pulse train signal. Its format is Ufix1_0. |
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| Step | If the corresponding option is activated, then an output port will be available to reuse the actual step-size. |
Characteristics and Limitations
| Direct Feedthrough | NO |
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| Discrete sample time | NO |
| XHP support | N/A |
| Work offline | NO |