The OP4610-IO expansion unit was designed with the Xilinx Kintex™-7 410T FPGA to provide additional inputs and outputs to OPAL-RT simulators.
The FPGA is used to execute models designed with OPAL-RT RT-XSG, manage I/O lines and execute embedded FPGA-based simulations.
It can be connected to OPAL-RT simulators via MUlti-System Expansion link (MuSE) or a PCIe link.

The combination of this versatile FPGA, with a high number of I/O lines (up to 144), and high-speed connectivity for communication with the OPAL-RT simulator and with third-party units under test (UUT), makes the OP4610-IO perfectly suited to I/O intensive simulations.

Features 

• Xilinx Kintex™-7 410T FPGA technology:
  • Programmed via MuSE or PCIe link.
  • The FPGA is used to execute models designed with the OPAL-RT RT-XSG tool, manage the I/O lines and execute embedded FPGA-based simulations.
  • It exchanges data with the real-time simulations running on the target computer CPUs via MuSE or PCIe link.
• Capable of controlling any combination of up to four (4) OP5300 Mezzanine Modules (analog or digital).
  • Each module controls 16 or 32 channels, for a total of up to 128 I/Os.
• 6 DI and 6 DO RS-422 I/Os for a total of 12 channels are installed by default.
  • Optional 6 DI and 6 DO Fiber-Optic Connector kit.
• 4 SFP ports for high-speed communication between FPGA-based systems or external devices.
• 1 free slot for optional PCIe add-in cards.

System Architecture

The figure below shows a block diagram showing the architecture of the OP4610-IO Expansion Unit.

Communication with the Master Unit 

The OP4610-IO can communicate with the simulator (or master unit) in three different ways:

• Using SFP socket (default communication means), see the section above.
• Using optional Dolphin SW-Link PCIe adapter
• Using optional PCIe Target Cable Adapter

By default, the communication link is using MuSE via one SFP socket, as illustrated in the figure below. Other free SFP sockets can be used to connect other devices.

Communication link via MuSE between an OP4610XG simulator and an OP4610-IO expansion unit

The figure below shows a diagram showing the architecture of the OP4610-IO Expansion Unit linked to an OP4610XG simulator acting as the primary device using a Dolphin SW-Link PCIe adapter or a PCIe Target Cable Adapter.
To communicate, both the simulator and the I/O expansion unit must have the same PCIe adapter card.

Communication link via Dolphin SW-Link PCIe adapter or PCIe Target Cable Adapter between an OP4610XG simulator and an OP4610-IO expansion unit

SFP Interconnection

The four SFP sockets allow interconnection with other OPAL-RT chassis or external devices, like amplifiers or MMC controllers.
The standard communication protocols available with the OP4610-IO are based on Xilinx Aurora (1 to 5 Gbps). 

There are two standard modes of operation available for the SFP ports, both based on the Xilinx Aurora communication protocol:

• Generic Aurora communication: this mode is enabled using the Generic Aurora blocks of the OPAL-RT RT-XSG toolbox.
  • These blocks are used to exchange data with third-party devices or with other OPAL-RT systems.
  • The data communication layer (data packing/unpacking) must be configured by the user according to the targeted application.
  • The communication speed is configurable between 1 and 5 Gbps and the SFP transceivers must be selected accordingly.

• OPAL-RT MUlti-System Expansion link (MuSE): this mode encapsulates the Aurora protocol within a network protocol designed by OPAL-RT for inter-system communication.
  • The communication speed is set to 5Gbps by default, but downgrades automatically to the speed of the other port, if that port is used at a lower speed for third-party device connection.
  • Only one SFP is used for the MuSE link, the other SFP ports remain available for the legacy Generic Aurora link.

Other protocols like the Gigabit Ethernet can also be implemented.