The OP5368 module features 8 bidirectional digital channels compliant with the RS-485 standard. It is available in three options, or kits, consisting of the OP5368 module itself and the FPGA support for different protocols:

• OP5368K1:  EnDat 2.2 protocol support

• OP5368K2: BiSS-C support

• OP5368K3: raw RS-485 support

Main Features

• 8 bidirectional channels

• Compliant with RS-485 electrical standard

• Support for raw RS-485 data transmission, EnDat 2.2 and BiSS protocols

Channel Description

The schematic below represents the electrical circuit of one channel. Three signals are managed by the FPGA of the simulator in which the module is installed: Rx input signal, Tx output signal, and a direction control signal.

From these signals, the module routing makes two RS-485 signals available for connection with the unit-under test (user side), which are either Rx+/Rx- or Tx+/Tx- depending on the direction selected for the targeted application.

Protocol Support

EnDat 2.2 (OP5368K1)

The EnDat 2.2 protocol is a digital, bidirectional interface standard from Heidenhain used to communicate with absolute digital position encoders. The EnDat 2.2 interface is a pure serial digital interface based on RS-485 standard.

When the OP5368 operates in EnDat 2.2 mode, only four encoder interfaces are available since each interface requires two differential signals: Two lines are used for the bidirectional differential data (DATA+ and DATA-) and are transmitted in half-duplex mode. The other two lines are used for the differential clock signal (CLOCK+ and CLOCK-)

The FPGA support implements the following EnDat specifications:

• Configurable encoder bus speed: 100kHz to 8MHz (in 200kHz increments)

• Clock frequency of 16 MHz with up to 20m cable length, and 8 MHz up to 100m cable length

• Encoder DC supply: 4 to 14V (must be provided externally)

• Absolute position encoder: single turn/multi-turn

• Configurable encoder position refresh rate

• Configurable encoder accuracy (bit width)

• Cable delay compensation

• Recovery time management (Tm, Tr, Tst)

BiSS (OP5368K2)

The BiSSinterface (for Bidirectional/Serial/Synchronous) is hardware-compatible with the industrial standard SSI (Serial Synchronous Interface) and is used in industrial applications to communicate with sensors and actuators. 

When the OP5368 operates in BiSS mode, only four encoder interfaces are available since each interface requires two differential signals: Two lines are used for the bidirectional differential data (DATA+ and DATA-) and are transmitted in half-duplex mode. The other two lines are used for the differential clock signal (CLOCK+ and CLOCK-)

The FPGA support implements the following BiSS specifications:

• Single turn/multi-turn encoder support

• Configurable encoder resolution: 8 to 40 bits (single turn = number of bits for the position, multi-turn = sum of the number of bits of position and revolution count)

• Configurable first transmission bit (MSB or LSB)

• Adjustable clock pulse frequency (62.5kHz - 1.5MHz)

• Position update rate up to 25kHz (master)

Typical Use Cases

The EnDat 2.2 (OP5368K1) and BiSS (OP5368K2) interfaces are used to communicate with absolute position encoders. The raw RS-485 support (OP5368K3) can be integrated with custom logic for customer-specific RS-485 communication applications.