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SPS WORKFLOW SCHEMATIC EDITOR WORKFLOW

Introduction

This firmware includes:

  • One eHS x128 Gen5 Solver

  • One Analog Output Mapping and Rescaling (AOMR) module

  • One Analog Input Differential Rescaling (AIR) module

  • One Thermal Losses (TL) module

  • One Saturable Transformer (satXFO) module


LoadIn/DataIn/DataOut mapping


LoadIn

DataIn

DataOut

1

Config eHS

Inputs eHS

eHS Averaged

2

Scenario / Rst eHS = Status

TSDO 1 - eHS 0 to 7

eHS DownSample

3


TSDO 2 - eHS 8 to 15

Digital In 1A - 0 to 7

4

PWM 1A -  0 to 7

TSDO 3 - eHS 16 to 23

Digital In 1A - 8 to 15

5

PWM 1A -  8 to 15

TSDO 4 - eHS 24 to 31

Digital In 1A - 16 to 23

6

PWM 1A -  16 to 23

TSDO 5 - eHS 32 to 39

Digital In 1A - 24 to 31

7

PWM 1A -  24 to 31

TSDO 6 - eHS 40 to 47

eHS Period Averaged

8


TSDO 7 - eHS 48 to 55

eHS Period DownSample

9


TSDO 8 - eHS 56 to 63

TimeOn Averaged

10


TSDO 9 - eHS 64 to 71

TimeOn DownSample

11


Digital Out 1B - SDO 0 to 7

Thermal Losses

12

Config AOMR

Digital Out 1B - SDO 8 to 15

Analog In 2A - 0 to 7

13

eHS PWM 1 - eHS 24 to 31

Digital Out 1B - SDO 16 to 23

Analog In 2A - 8 to 15

14

eHS PWM 2 - eHS 0 to 7

Digital Out 1B - SDO 24 to 31


15

eHS PWM 3 - eHS 8 to 15



16

eHS PWM 4 - eHS 16 to 23



17

Config eHS AIR



18




19


AOMR/ Analog Out 2B -  0 to 7


20


Analog Out 2B -  8 to 15


21

Config Thermal Losses



22

SFP



23

Lookup Table Config

eHS PWM 1 -  0 to 7


24


eHS PWM 2 -  8 to 15


25


eHS PWM 3 -  16 to 23


26


eHS PWM 4 -  24 to 31


27


eHS SWG


28




29




30




31




32




33


Thermal Losses


34


SFP


35


LED



System Overview


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eHS solver

SPS WORKFLOW SPECIFIC

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Connectivity

SPS WORKFLOW SPECIFIC

Source Type

Source Index

Source Name

Details

Input

0

CPU Input


1

eHS Analog In

Slot 2A - Ch00-15

2

Data stream from SFP #00


3

Sine Wave Generator


Gate

0

Digital Input

Slot 1A - Ch00-31

1

PWM


2

CPU Gating Signal

TSDO 0-32

SPS WORKFLOW SPECIFIC

To contextualize the Input and Gate Configuration table with this firmware configuration, the eHS firmware config tab must be configured with the following custom input source enumeration:

{'CPU Model',0,128;'Sine Wave Generator',3,32;'Analog In',1,16;'SFP',2,32}

And this custom gate sources enumeration:

{'CPU Model',2,32;'Digital Inputs',0,32;'PWM',1,32}



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Communication port configuration for the Thermal Losses (TL) block


Thermal Losses

Data In Port Number

33

Load In Port Number

21

Data Out Port Number

11



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Communication port configuration for the Analog Output Mapping and Rescaling (AOMR) block


AOMR - Slot 2B

Version

V2

Data In Port Number

19

Load In Port Number

12



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Communication port configuration for the Analog Input Differential Rescaling (AIR) block


AIR - Slot 2A

Channels

Ch00-15

Load In Port Number

17

AOMR Output

Lane Index

Signal Source

Details

0

eHS Outputs

eHS Y01-128

5

Data Stream from SFP #01




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Communication port configuration for the SFP mapping and communication block


SFP - Channel 0

Data In Port Number

34

Load In Port Number

22



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Communication port configuration for the Analog Input (AI) block


Slot 2A 

Channels

Ch00-07

Ch08-15

Data Out Port Number

12

13

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment



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Communication port configuration for the Analog Output (AO) block


Slot 2B

Channels

Ch00-07

Ch08-15

Data In Port Number

19

20

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment



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Communication port configuration for the Digital Input (DI) block


Slot 1A 

Channels

Ch00-07

Ch08-15

Ch16-23

Ch24-31

Data Out Port Number

3

4

5

6

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment



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Communication port configuration for the Digital Output (DO) block


Slot 1B 

Channels

Ch00-07

Ch08-15

Ch16-23

Ch24-31

Data In Port Number

11

12

13

14

Load In Port Number

4

5

6

7

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment





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