Each gate signal required to control the machine inverter should be connected to a Digital Input channel of the OPAL-RT Simulator. The digital input channels are interfaced with the eHS directly within the FPGA firmware.
Once the Inverter model is created, and the list of switches is known, the user can select which digital input should be mapped to each switch of the model.
To do so, the eHS CPU block provides a user interface in the Gates settings tab of the eHS Simulink mask. To open the mapping UI, the “Switch control source” must be set as Independent setting for each element.
By checking the checkbox, the Gate control selection Panel will open.
For each switch, the user can select the control type. To map a digital input channel, select the Switch control type as “From Digital Inputs”, then specify the channel by editing the Index value.
For simulator with one digital input I/O module, the Index is equal to the channel number (zero-based from 0 to 31).
For simulator with multiple Digital input modules, the index is the channel number of the module but offset by 32 for the second digital input module, 64 for the third, 96 for the fourth etc…
For example, if a chassis has the configuration bellow:
| Section A | Section B | |
|---|---|---|
| Slot 1 | OP5330-3 16 Analog Output channels 1MSPS | OP5340 16 Analog Inputs 500KSPS |
| Slot 2 | OP5353 32 Digital Input channels | OP5353 32 Digital Input channels |
| Slot 3 | OP5330-3 16 Analog Output channels 1MSPS | OP5330-3 16 Analog Output channels 1MSPS |
| Slot 4 | OP5353 32 Digital Input channels | OP5360-2 32 Digital Output channels |
There is 3 digital input module (2A, 2B, and 4A). The indexes 0 to 31 will be reserved for channels 0 to 31 of the digital input module in 2A, the indexes 32 to 63 will be reserved for channels 0 to 31 of the digital input module in 2B, and the indexes 64 to 96 will be reserved for channels 0 to 31 of the digital input module in 4A.