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V2.20 Official Firmware Documentation
Software Requirements
General Firmware list
Legend Status | SE Available in Schematic Editor Workflow SPS Available in Simscape Electrical Specialized Power Systems (SPS) Workflow | SE* Custom Schematic Editor Workflow * Custom firmware descriptions allow external models to be integrated into the Schematic Editor S-function Workflow. |
Important note
Extra costs might apply for custom and non-standard firmware.
OP4810 - OP4815 | ||||||||
---|---|---|---|---|---|---|---|---|
Part Number | Details | Version | Generation | eHS licence class | Machines | Miscellaneous Features | Quad Encoder Resolver | Bitstream |
| 1.3.4 | Gen5 SE | x128 x64 x32 x16 |
| FPGA Scope |
| OP5145_2-EX-0001-3_7_0_819-eHSx128_Gen5_PowerElectronics_IOConfig1-5A-24 | |
OP4815_500Mhz_eHS_Gen5_x128_Machines_IOConfig1 | ||||||||
| 1.0.2 | Gen5 SE | x128 x64 x32 x16 |
| FPGA Scope |
| OP5145_2-EX-0001-3_7_0_819-eHSx128_PowerSystems_FDLine_IOConfig1-2A-04 | |
OP4815_500Mhz_eHS_Gen5_x128_PowerSystems_FDLine_IOConfig1 | ||||||||
| OP4815 - eHS | 1.0.0 | Gen5 SE | x128 x64 x32 x16 |
| FPGA Scope |
| OP5145_2-EX-0001-3_7_0_819-eHSx128_Gen5_MachineDrive_IOConfig2-1D-02 |
OP4815_500Mhz_eHS_Gen5_x128_MachineDrive | ||||||||
| 1.0.1 | Gen5 SE | x128 x64 x32 x16 |
| FPGA Scope |
| OP5145_1-EX-0001-3_6_0_818-eHSx128_Gen5_Machines_IOConfig1-1A-32 | |
OP4810_500Mhz_eHS_Gen5_x128_Machines_IOConfig1 | ||||||||
| 1.0.2 | Gen5 SE | x128 x64 x32 x16 |
| FPGA Scope |
| OP5145_1-EX-0001-3_7_0_819-eHSx128_Gen5_MachineDrive_IOConfig2-1B-02 | |
OP4810_500Mhz_eHS_Gen5_x128_MachineDrive |
OP5707 - OP5607 | ||||||||
---|---|---|---|---|---|---|---|---|
Part Number | Details | Version | Generation | eHS licence class | Machines | Miscellaneous Features | Quad Encoder Resolver | Bitstream |
FW300-V71 | 1.13.0 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| VC707_2-EX-0001-3_7_0_819-eHSx128_Gen4_Machines_IOConfig1-35-62 | |
OP5607_300_eHS_Gen4_x128_Machines_SE_withIOs_rtxsg | ||||||||
FW300-V71 | 1.5.0 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| VC707_2-EX-0001-3_7_0_819-eHSx128_Gen4_Induction_Machines_IOConfig1-40-2E | |
OP5607_300_eHS_Gen4_x128_Induction_Machines_SE_withIOs_rtxsg | ||||||||
FW301-V71 | 1.10.0 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| VC707_2-EX-0001-3_7_0_819-eHSx128_Gen4_PMSMSH_IOConfig1-03-1D | |
OP5607_300_eHS_Gen4_x128_PMSMSH_SE_withIOs_rtxsg | ||||||||
|
| 1.1.0 | Gen5 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| VC707_2-EX-0001-3_7_0_819-eHSx128_Gen5_MachineDrive_IOConfig3-4D-02 |
OP5607_300_eHS_Gen5_x128_PMSMs_SE_withIOs_rtxsg | ||||||||
| 1.5.0 | Gen5 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| VC707_2-EX-0001-3_7_0_819-eHSx128_Gen5_PowerElectronics_IOConfig3-55-54 | |
OP5607_300_eHS_Gen5_x128_Machines_SE_withIOs_rtxsg | ||||||||
| 1.1.0 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| VC707_2-EX-0001-3_7_0_819-eHSx128_Gen4_PowerSystems_FDLine_IOConfig1-2C-4C | |
OP5607_eHSx128_PowerSystems_FDLine_IOConfig1_rtxsg | ||||||||
1.1.1 | Gen4 SE* SPS | x128 x64 x32 x16 |
| FPGA Scope |
| VC707_2-EX-0001-3_3_5_809-eHSx128_Gen4_Motors_with_IOs-53-12 | ||
OP5607_300_eHSx128Gen4_withMotorsAndIOs |
OP4512/OP4610 | ||||||||
---|---|---|---|---|---|---|---|---|
Part | Details | Version | Generation | eHS licence | Machines | Miscellaneous Features | Quad Encoder Resolver | Bitstream |
| 1.7.2 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| TE0741_4-EX-0001-3_5_0_817-eHSx128_Gen4_Machines_IOConfig2-3C-17 | |
OP4510_400_eHS_Gen4_x128_Machines_SE_IOConfig2_rtxsg | ||||||||
| 1.0.0 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| TE0741_4-EX-0001-3_7_0_819-eHSx128_Gen4_Machines_IOConfig1-0E-7A | |
OP4510_400_eHS_Gen4_x128_Machines_SE_IOConfig1_rtxsg | ||||||||
| 1.4.5 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| TE0741_4-EX-0001-3_5_0_817-eHSx128_Gen4_Induction_Machines_IOConfig2-22-2D | |
OP4510_400_eHS_Gen4_x128_Induction_Machines_SE_IOConfig2_rtxsg | ||||||||
| 1.6.2 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| TE0741_4-EX-0001-3_5_0_817-eHSx128_Gen4_PMSMSH_IOConfig2-3E-15 | |
OP4510_400_eHS_Gen4_x128_PMSMSH_SE_IOConfig2_rtxsg | ||||||||
| 1.6.1 | Gen5 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| TE0741_4-EX-0001-3_7_0_819-eHSx128_Gen5_PMSM_IOConfig2-FB-22 | |
OP4510_400_eHS_Gen5_x128_Machines_SE_IOConfig2_rtxsg | ||||||||
| 1.0.0 | Gen5 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| TE0741_4-EX-0001-3_7_0_819-eHSx128_Gen5_Power_Electronics_IOConfig1-B1-76 | |
OP4510_400_eHS_Gen5_x128_Machines_SE_IOConfig1_rtxsg | ||||||||
| 1.0.5 | Gen4 SE SPS | x128 x64 x32 x16 |
| FPGA Scope |
| TE0741_4-EX-0001-3_5_0_817-eHSx128_Gen4_PowerSystems_FDLine_IOConfig2-1C-05 | |
OP4510_eHSx128_PowerSystems_FDLine_IOConfig2_rtxsg | ||||||||
| N/A | Gen4 SE* SPS | x64 x32 x16
|
| FPGA Scope |
| TE0741_4-EX-0001-3_2_10_45-eHSx64gen4_PMSMSH_with_IOs-41-04 | |
OP4510_400_eHSGen4_Motors_PMSMSH_withIOs_rtxsg |
OP4510 - Legacy | ||||||||
---|---|---|---|---|---|---|---|---|
Part Number | Details | Version | Generation | eHS licence class | Machines | Miscellaneous Features | Quad Encoder Resolver | Bitstream |
FW303-K31 | 1.11.0 | Gen4 SE SPS | x64 x32 x16 |
| FPGA Scope |
| TE0741_3-EX-0001-3_4_0_814-eHSx64_Gen4_Machines_IOConfig1-3B-48 | |
OP4510_300_eHS_Gen4_x64_Machines_SE_IOConfig1_rtxsg | ||||||||
| 1.7.0 | Gen4 SE SPS | x64 x32 x16 |
| FPGA Scope |
| TE0741_3-EX-0001-3_4_0_814-eHSx64_Gen4_Machines_IOConfig2-3F-13 | |
OP4510_300_eHS_Gen4_x64_Machines_SE_IOConfig2_rtxsg | ||||||||
FW304-K31 | 1.9.0 | Gen4 SE SPS | x32 x16 |
| FPGA Scope |
| TE0741_3-EX-0001-3_4_0_814-eHSx32_Gen4_PMSMSH_IOConfig1-02-16 | |
OP4510_300_eHS_Gen4_x32_PMSMSH_SE_IOConfig1_rtxsg | ||||||||
| 1.1.1 | Gen4 SE* SPS | x64 x32 x16 |
| FPGA Scope |
| TE0741_3-EX-0001-3_3_6_811-eHSx64_Gen4_Motors_with_IOs-43-09 | |
OP4510_300_eHSGen4_Motors_PMSMVDQ_withIOs_rtxsg | ||||||||
| 1.0.0 | Gen4 SPS | x64
|
| FPGA Scope |
| TE0741_3-EX-0001-3_3_2_804-eHSx64_Gen4_PMSMSH_with_IOs-44-08 | |
OP4510_300_eHSGen4_Motors_PMSMSHnoSRM_withIOs_rtxsg |
Standard IO config
Hardware | Description | Slot 1A | Slot 1B | Slot 1C | Slot 1D | Slot 2A | Slot 2B | Slot 2C | Slot 2D | IO Extension |
---|---|---|---|---|---|---|---|---|---|---|
|
| OP48H10 | N/A | OP48H10 | N/A |
| ||||
OP4815 OP4810 | 32 DIO | 16 AO | 16 AI | N/A | 32 DIO | 16 AO | 16 AI | N/A | RS422 6DI 6DO | |
|
| OP48H20 | OP48H20 |
| ||||||
OP4815 OP4810 | 16 DI | 16 DO | 24 AO 1MSPS 12 AO 2 MSPS | 8AI | 16 DI | 16 DO | 24 AO 1MSPS 12 AO 2 MSPS | 8AI | RS422 6DI 6DO | |
|
| OP48H30 | OP48H30 |
| ||||||
OP4815 OP4810 |
| 32 AO | 32 DIO | 16 AO 16 AI | 32 DIO |
|
|
|
|
|
Hardware | Description | Slot 1A | Slot 1B | Slot 2A | Slot 2B | Slot 3A | Slot 3B | Slot 4A | Slot 4B | IO Extension |
---|---|---|---|---|---|---|---|---|---|---|
OP5707 - OP5607 OP5650 | 16 AO - OP5330-3 | 16 AI - OP5340 | 32 DI - OP5369(2) | 32 DO - OP5369(2) | 16 AO - OP5330-3 | 16 AO - OP5330-3 | 32 DI - OP5369(2) | 32 DO - OP5369(2) | n/a | |
OP5707 - OP5607 OP5650 | 16 AO - OP5330-3 | 16 AI - OP5340 | 32 DIO - OP5369(2) | 32 DIO - OP5369(2) | 16 AO - OP5330-3 | 16 AO - OP5330-3 | 32 DI - OP5369(2) | 32 DO - OP5369(2) | n/a | |
OP5707 - OP5607 OP5650 | 16 AO - OP5330-3 | 16 AI - OP5342 | 32 DI - OP5369(2) | 32 DO - OP5369(2) | 16 AO - OP5330-3 | 16 AO - OP5330-3 | 16 AO - OP5330-3 | 32 DO - OP5369(2) | n/a | |
OP5707 - OP5607 OP5650 | 16 AO - OP5330-3 | 16 AI - OP5342 | 32 DIO - OP5369(2) | 32 DIO - OP5369(2) | 16 AO - OP5330-3 | 16 AO - OP5330-3 | 16 AO - OP5330-3 | 32 DO - OP5369(2) | n/a | |
OP4510 | 32 DIO - OP5369(2) | 32 DIO - OP5369(2) | 16 AI - OP5340 | 16 AO - OP5330-3 | n/a | n/a | n/a | n/a | RS422 6DI 6DO | |
OP4510 | 32 DIO - OP5369(2) | 16 AO - OP5330-3 | 16 AI - OP5342 | 16 AO - OP5330-3 | n/a | n/a | n/a | n/a | RS422 6DI 6DO |
(1) Only supported with S-Function Driver
(2) Despite the bi-directional capability of OP5369, each configuration can be single direction because of FPGA capability
Compatible IO config
All above mentioned firmwares support the "Polymorphism" feature. The cards listed here are compatible at the same location/slot.
To activate the Polymorphism, the parameter "Disable strict hardware mismatch validation" must be set to true in the FPGA configuration (OPAL-RT Board or OpCtrl)
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