Block
Mask
Description
This block implements the IEC60044-8 protocol between a valve balancing controller (VBC) and a pole controller based on HDLC serial protocol . This is the communication unit used in the VB or Pole controller.
| bit | 15:0 |
|---|---|
| H | 0x0564 |
| R0 | Block 1 Data R0 |
| R1 | Block 1 Data R1 |
| R2 | Block 1 Data R2 |
| R3 | Block 1 Data R3 |
| R4 | Block 1 Data R4 |
| R5 | Block 1 Data R5 |
| R6 | Block 1 Data R6 |
| R7 | Block 1 Data R7 |
| CRC | |
| R0 | Block 2 Data R0 |
| R1 | Block 2 Data R1 |
| R2 | Block 2 Data R2 |
| R3 | Block 2 Data R3 |
| R4 | Block 2 Data R4 |
| R5 | Block 2 Data R5 |
| R6 | Block 2 Data R6 |
| R7 | Block 2 Data R7 |
| CRC | |
| ... | ... |
| R0 | Block N Data R0 |
| R1 | Block N Data R1 |
| R2 | Block N Data R2 |
| R3 | Block N Data R3 |
| R4 | Block N Data R4 |
| R5 | Block N Data R5 |
| R6 | Block N Data R6 |
| R7 | Block N Data R7 |
| CRC |
Parameters
| Sample Period | This is a non-modifiable parameter. It is used to specify the FPGA clock period. |
|---|
Inputs
| HDLC Serial DataIn | This is the serialized data link received from the PCP/VBC unit, moduled with Manchester encoding and sent using the IEC60044-8 standard as defined by the HDLC-1/HDLC-2 byte assignation. | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Start transfer | This port is used to start a transmission. When activated the following 9 input signals are registered and then sent on the serial link using the IEC60044-8 standard as defined by the HDLC-2 byte assignation. | ||||||||||||||||||
| Number Of Block | This port is used to specify the number of block in the current HDLC frame (see Characteristics and Limitations for more details). | ||||||||||||||||||
| DataIn Block[X] where X = [1 to 15] | This is a 128 bits wide Data Block in the transmit HDLC frame (see Characteristics and Limitations for more details). When writing to this port, users must place data in this format:
|
Outputs
| HDLC Serial DataOut | This is the serialized data link transmitted to the PCP/VBC unit, moduled with Manchester encoding and sent using the IEC60044-8 standard as defined by the HDLC-1/HDLC-2 byte assignation. | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DataOut Valid | A full packet of new data has just been received. This is simply a 1-cycle pulse activated once all data is registered on the outputs. | ||||||||||||||||||
| DataOut Block[X] where X = [1 to 15] | This is a 128 bits wide Data Block in the received HDLC frame (see Characteristics and Limitations for more details). The table below shows how received data are formatted for each data block.
|
Characteristics and Limitations
The current IEC60044-8 is a length-flexible frame. The range of data BLOCK carried in each frame is from 1 to 15. Every Block includes 16 Bytes. CRC checksum is computed for each Block. The initial value of the 16-Bit verification sequence generated by this criterion is 0x0000 and the calculating result is bitwise negated.
The "Start Transfer" input signal is typically fed by a pulse train generated with an interval of 100 microseconds between pulses.
| Direct Feedthrough | N/A |
|---|---|
| Discrete sample time | N/A |
| XHP support | N/A |
| Work offline | NO |