Location
This example model can be found in the HYPERSIM under the category "Transmission" with the file name "FPGA-BASED_Half-Line_CPU-eHS.ecf".
Description
The multirate half line model is employed to decouple two discretized systems using an inductor. The equations are similar to a PI-line section. In this example model, the goal is to use half lines to decouple the model into 2 sections one implemented on FPGA/eHS and the other one implemented on CPU/HYPERSIM. The half line is transmission line for which the user can select the total inductance and resistance. Used with transformers, the half line can often substitute for the secondary leakage inductance and provide a decoupling delay in the global systems of equations. In real-time applications, this enables the parallelization of the computations on different CPU cores. Even in a single core or in offline simulation, the half line can increase simulation performance because it creates a delay between state-space systems on each side of it.
In this example, a rectifier circuit is fed by 3-winding transformer, configured as star-star-delta (Y-Y-Δ). The combination of these two sets of voltages results in a total of six phases (three from each transformer secondary winding) entering the rectifier circuit. This arrangement effectively increases the number of pulses in the rectified output, leading to harmonic cancellation and reduced ripple in the DC output. Also, the multirate half lines, transmission line of 3-time-step length, is used with transformers, it can replace primary leakage inductance and introduce decoupling delay in global equation systems.
Requirements
The HYPERSIM, Schematic Editor/Unified Database, and eFPGASIM toolboxes must be installed on the host and target computers to run this example model properly. Please refer to the product documentation for details on version compatibility. Also, the minimal time step in this example is 10 µs. When using a different sampling time, it is important to update the half-line parameters
Setup and Connections
For this example model, Schematic Editor and I/Os need to be configured.
Half-line Block Configurations
Name | Description | Unit | |
|---|---|---|---|
Half stubline model | Use inductance only or Use capacitance only, whether the half-line should be used as an inductance or a capacitance | - | |
Inductance | Inductance value when “Use inductance only” is choosen | H | |
Capacitance | Capacitance value when “Use inductance only” is choosen | F | |
Round trip latency | Communication latency for the round trip delay from HYPERSIM to eHS and back to HYPERSIM. Typically 3 times the sampling time of HYPERSIM | s | |
Schematic Editor Configurations
In Schematic Editor, the target needs to be properly set:
Click on your firmware configuration at the bottom left of Schematic Editor.
Select or create your simulation setup. Note that all FPGA Firmware support the Half Line Model.
Click on the Solver Settings button next to your firmware configuration button.
Define your solver settings for the simulation.
The example model in HYPERSIM is reproduced in Schematic Editor. See the figure below. The half-line has to be configured as it is done in HYPERSIM model.
IO Configuration
Since part of the simulation is done through eHS, it is required to connect HYPERSIM to it. Here are the steps for that configuration:
Open the I/O Interface Configuration
Add an OPAL-RT Board
Select the correct Chassis ID. This example uses an OP4610XG (Kintex-7) target.
Select Optical for the type of generated synchronization signal.
Select Standard repositories for the bitstream configuration location, then select your bitstream configuration file. In this example, the bitstream configuration file is
TE0741_41_4-EX-0001-eHSx128_Gen4MachinesIOConfig2.opal
And the bitstream name is
TE0741_4-EX-0001-3_5_0_817-eHSx128_Gen4_Machines_IOConfig2-3C-17.bin
Simulation and Results
The simulation has been executed and results have been recorded. The figure below presents currents from the main voltage source to the different lines, respectively from Reference (without decoupling elements displayed in red), CPU (displayed in blue) and eHS (displayed in green). This figure also displays the DC voltage passed the rectifier for each line, respectively again from Reference (without decoupling elements), CPU and eHS.
In the figure below, the focus is on the comparison of results obtained in HYPERSIM vs eHS during the opening of a switch on the line at t = 0.5 s. The system remains balanced in a steady state before the event occurs at t = 0.5 s. Due to the decoupling between CPU/FPGA a small error is introduced and this limitation can be mitigated by choosing a larger inductance or location with a slower dynamic.