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Expand each of the sections below to explore the parameters configured in the SCIM With Saturation example. The information on this page can also be used to validate project settings or to re-create the example in a new VeriStand project.

Example Directory

<Public Documents>\National Instruments\<NI VeriStand 20xx>\Examples\OPAL-RT\Power Electronics Add-On\SCIM With Saturation

Project Path

<SCIM With Saturation>\Project\SCIM With Saturation.nivsprj

 Opening the Example

Opening the Example

  1. To avoid modifying the original example, make a local copy of the Example Directory shown above.

  2. Open VeriStand and Browse to the copied directory, then continue browsing to the Project Path and select the VeriStand Project (.nivsprj) file.

  3. Click Configure... to open the System Definition file.

  4. See the following sections on this page to explore the parameters configured in the Configuration Tree of the System Definition file.

 Hardware Configuration

Hardware Configuration

  1. In the Configuration Tree, expand Controller >> Custom Devices and click the Power Electronics Add-On custom device to open its configuration page.

  2. The eHSx64_Quad_IM_Saturation_IO_7868R hardware configuration is selected in the Configuration dropdown.

 Circuit Model, Sources, and Switches

Circuit Model

The Circuit Model in this example serves as a simple three-phase voltage source for the machines. The Sources are controlled by the same set of three Sinewave Generators, while the phase voltage Measurements are mapped to the voltage inputs of both IM with Saturation machine models.

  1. In the Configuration Tree, expand Power Electronics Add-On and click Circuit Model.

  2. The Circuit Model File Path points to the currently loaded Circuit Model. Open the file in Simulink to observe the circuit.

  3. (optional) Click Reload to trigger a model update in the System Definition.

  4. (optional) Click the Refresh button to see additional model information.

Circuit Model File Path: <SCIM With Saturation>\Circuit Model\SCIM_eHS_Passthrough.slx

Sources

The Sources page maps signals to each source of the circuit model. In this example, the machine phase currents are fed back to the circuit. The six AC voltage sources are controlled using three Sinewave Generators.

  1. In the Configuration Tree, expand Circuit Model and click Sources. This page is populated with a list of sources from the circuit model.

  2. The mappings are configured as shown below.

Switches

The Switches page maps signals to each switch of the circuit model. In this example, a single dummy switch is used to meet the minimum requirements of the eHS solver. The switch mapping configuration does not affect the results of the simulation.

  1. In the Configuration Tree, expand Circuit Model and click Switches. This page is populated with a list of switches from the circuit model.

  2. The mappings are configured as shown below; any Group and Element can be mapped to the switch.

 Machine Model

Electric Model

In this example, two IM with Saturation models are configured using identical electrical parameters, but different Magnetizing Inductance files. The first model simulates an induction machine with a typical saturation profile, while the second model simulates a standard induction machine with no saturation.

  1. In the configuration tree, expand Circuit Model and click IM with Saturation 1 and IM with Saturation 2 to open the configuration pages for the machines.

  2. A different Magnetizing Inductance File Path is configured for each of the two machines:

IM with Saturation 1

<SCIM With Saturation>\Magnetizing Inductance\MagnetizingInductance_withSaturation.json

IM with Saturation 2

<SCIM With Saturation>\Magnetizing Inductance\MagnetizingInductance_withoutSaturation.json

  1. The other Machine Configuration parameters and the Input Mapping Configuration parameters of both machines are configured identically, as summarized below.

Machine Configuration

Machine Type

Squirrel-Cage Induction Machine

Stator Resistance (Ohm)

0.087

Stator Leakage Inductance (H)

0.000801061

Rotor Resistance (Ohm)

0.228

Rotor Leakage Inductance (H)

0.000801061

Pole Pairs

2

Magnetizing Inductance Cutoff Frequency (Hz)

3000

Synchronous Reference Frame Orientation

Stator Flux

Synchronous Reference Frame Offset (Deg)

0

Stator Rotor Turn Ratio

1

Rotor Temperature Coefficient

0

Stator Temperature Coefficient

0

Input Mapping Configuration

Stator Voltage Phase A (IM with Saturation 1)

Circuit Model 1.Va_l-n

Stator Voltage Phase B (IM with Saturation 1)

Circuit Model 1.Vb_l-n

Stator Voltage Phase C (IM with Saturation 1)

Circuit Model 1.Vc_l-n

Stator Voltage Phase A (IM with Saturation 2)

Circuit Model 1.Vx_l-n

Stator Voltage Phase B (IM with Saturation 2)

Circuit Model 1.Vy_l-n

Stator Voltage Phase C (IM with Saturation 2)

Circuit Model 1.Vz_l-n

Mechanical Model

  1. In the configuration tree, expand IM with Saturation 1 and IM with Saturation 2, then click Mechanical Model to view their respective mechanical model parameters.

  2. The Initial Values and Configuration parameters are configured as summarized below.

  3. In the configuration tree, expand each Mechanical Model and click the Mechanical Model Mode channel.

  4. The Default Value of each Mechanical Model Mode channel is set to 1 (Torque Controlled).

Initial Values

Initial Rotor Angle (Deg)

0

Mechanical Model Configuration

Viscous Damping

0.006

Static Friction

0

Inertia

1.662

Mechanical Model Mode (VeriStand Channel)

1

 Signal Generators

Sinewave Generators

In this example, the FPGA-based Sinewave Generators drive the six AC voltage sources of the Circuit Model.

  1. In the configuration tree, expand Circuit Model and click Sinewave Generators.

  2. The default channel values for SWG 0, SWG 1, and SWG 2 are configured as summarized below.

Frequency Engines

Channel Name

Default Value

Frequency Engine 0

60Hz

SWG 0

Channel Name

Default Value

Frequency Engine

0

Phase

SWG 1

Channel Name

Default Value

Frequency Engine

0

Phase

-120º

SWG 2

Channel Name

Default Value

Frequency Engine

0

Phase

120º

 Waveform Channels

Waveform Channels

Waveform Channels allow signals to be streamed from the FPGA at a rate faster than that of the CPU execution.

  1. In the Configuration Tree, expand Circuit Model and click Waveforms.

  2. The signals in the example are mapped to the Waveform channels as shown below. The data from these channels will be streamed at the Sample Rate (S/s) specified at the bottom of the page.

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