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HYPERSIM Release Notes: 2025.2
- 1 HYPERSIM 2025.2.1 - minor update
- 1.1 I/O Interfaces
- 1.1.1 OPAL-RT Board
- 1.1.2 Synchronization
- 1.1 I/O Interfaces
- 2 HYPERSIM 2025.2.0 - initial release
- 2.1 Software Toolboxes Installed with HYPERSIM
- 2.2 New features
- 2.3 Improvements
- 2.4 Bug fixes
- 2.5 Signal Visualization and Processing
- 2.5.1 Dashboards
- 2.6 Unified Database
- 2.6.1 PSCAD import
- 2.6.2 PowerFactory import
- 2.7 I/O Interfaces
- 2.7.1 CAN
- 2.7.2 IEC 60870-5-104 Slave
- 2.7.3 IEC 61850
- 2.7.4 MODBUS Master
- 2.7.5 OPAL-RT Board
- 2.7.6 Synchronization
- 2.8 FPGA-Based Power Electronics Toolbox
- 2.8.1 eHS Blockset
HYPERSIM 2025.2.1 - minor update
I/O Interfaces
OPAL-RT Board
Fixed simulation crash when I/O interface was configured to be the hardware synchronization source of the model and it was using an external synchronization source (master with external clock mode).
Fixed loss of connections made with a remote’s data points when its name was changed.
Synchronization
Fixed Oregano card initialization in 1PPS and IRIG-B modes.
HYPERSIM 2025.2.0 - initial release
Software Toolboxes Installed with HYPERSIM
Toolbox | Version Number |
|
|---|---|---|
v3.0.1 |
|
New features
A new preference has been introduced to enforce strict version matching between the host and target when starting a simulation. This check is enabled by default, ensuring that simulations will now fail to start if the target is running a different HYPERSIM version than the host, helping to prevent potential incompatibility issues.
The Data Logger API now supports Python versions 3.11, 3.12, and 3.13.
HyWorks API does not yet support these versions.
Improvements
Users can now open and edit models in HYPERSIM even if the host license has 0 cores enabled. Simulation remains unavailable, but model editing is now accessible.
When attempting to update a UCM using an unchanged definition file, the warning popup now includes a "Force Update" button. This allows users to proceed with the update even when no changes are detected.
The free space validation before installing HYPERSIM now accounts for external tools installed alongside the software.
The Python API function
displayDevicenow shows expressions on attributes.The https://opal-rt.atlassian.net/wiki/pages/createpage.action?spaceKey=pdochs&title=ScopeView%20%7C%20Templates&linkCreation=true&fromPageId=1387921479 now includes documentation for the “Save using relative path” option, which allows templates to reference recordings located next to the model using relative paths.
Rework the https://opal-rt.atlassian.net/wiki/spaces/PDOCHS/pages/149947197 model in HYPERSIM for consistent Loadflow results.
The https://opal-rt.atlassian.net/wiki/spaces/PDOCHS/pages/1150812780 has received many improvements:
Multicore support for real-time simulation. New ePHASORSIM Interface parameters allows the user to specify a desired number core for parallel computation done in the solver. The system choses which core to assign.
I/Os are now exposed as bundles.
The https://opal-rt.atlassian.net/wiki/spaces/PDOCHS/pages/1150845258 model was updated to benefit from bundles.
Improved UI/UX for displaying errors, block creation field validation and user feedback
ePHASORSIM logs can be now found in
%USERPROFILE%/HYPERSIM/log
Bug fixes
Fixed an issue where the https://opal-rt.atlassian.net/wiki/spaces/PDOCHS/pages/150079941 component was not getting updated when edited after Analyze.
Fixed the https://opal-rt.atlassian.net/wiki/spaces/PDOCHS/pages/149719120 component to correctly disable code changes during simulation.
Fixed an issue where the wrong eFPGASIM version was used after installing a different HYPERSIM/RTLAB version.
Fixed help buttons that were not working correctly when linked to documentation pages containing special characters.
Fixed an issue with https://opal-rt.atlassian.net/wiki/spaces/PDOCHS/pages/149523072 connections to the FPGA when the input/output name in Schematic editor contained forbidden characters in HYPERSIM schematic, such as white spaces.
Fixed dashboards compatibility on hosts running Windows Server.
Fixed an issue where eFPGASIM models containing signal names with special characters (e.g., spaces) could cause errors.
Fixed an issue where parameters of an UCM were not validated during Analyze.
Fixed a crash during Analyse with imported PSCAD models having components with long name.
Fixed an issue where updating some parameters on lines and cables during a simulation could cause unexpected errors on the target.
Signal Visualization and Processing
Dashboards
Unified Database
Added error handling for project access issues in 3rd party protected folders (Anti-Virus or cloud storge software)
PSCAD import
Improved the parsing of
number of phasesto function with subcircuitsImproved
computations(computed params) managementImproved visual representation of Datatap to Datamerge after import
Fixed
SOURCE_3mappingFixed the unit conversion of parameters that are referencing
Global Parameters
PowerFactory import
Fixed mapping issues for the Three Phase Two Winding transformer
Fixed mapping of
uelinparameter for ExcESST1AFixed mapping synchronous machines (ElmSym) without composite frames (ElmComp)
I/O Interfaces
CAN
Fixed simulation crash when unused multiplexed messages were present in the configuration.
Fixed transmission and reception of multiplexed messages.
IEC 60870-5-104 Slave
Improved point addition mechanism to avoid duplicating addresses.
Improved point duplication mechanism to retain the direction.
Improved the RMS (Root Mean Square) computation logic to ensure continuity even when in data loss scenarios.
IEC 61850
Fixed Sampled Values default sampling rate unit to be "samples per cycle".
MODBUS Master
Improved configuration validation in TCP mode by taking the slave ID into account.
OPAL-RT Board
Added support for eHS running on a MuSE remote platform.
Added a simplified command to manually program ARM-based FPGAs (OP4810-IO, OP4815-IO and OP4300-IO).
Added the display of extra information such as the IP and MAC addresses to the detection of OP4300-IO MuSE remote platforms.
Improved bitstream programming logs during the load of the simulation.
Improved description of digital IOs for the OP4300-IO platform.
Fixed the analog out voltage range drop-down behaviour.
Fixed loss of remotes configuration when switching the central chassis type to "OP5143 FPGA module (Artix-7)".
Fixed programming of remote MuSE bitstreams requiring non-default (different from 5 Gbps) SFP line speeds.
Synchronization
Fixed simulation crash when the Oregano card's network interface was configured to 'auto'.