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Example | OP4810-IO/OP4815-IO with OP48H30
Page Contents
Location
This example model is available in the software under the "IO Interfaces" category, with the file name: OP4810_OP4815_Integration_OP48H30.ecf.
Description
This example project demonstrates how to use the OPAL-RT Board interface to interact with the various I/O types—Analog, Static Digital, Pulse Width Modulation (PWM), and Time-Sampled Digital (TSD)—provided by the OP48H30 High Density I/O module. Two OP48H30 modules can be mounted in an OP48XX FPGA expansion chassis, such as the OP4810-IO or OP4815-IO.
More information can be found in the Hardware Products Documentation about OPAL-RT hardware products:
To execute this example project, you will need:
One OPAL-RT Simulator, that supports I/O expansion chassis.
One OP48XX expansion chassis, with two OP48H30 modules.
One PCIe cable, between the OPAL-RT Simulator and the OP48XX expansion chassis.
Two Ethernet cables:
One between the OPAL-RT Simulator and the Windows Host network.
One between the OP48XX expansion chassis and the Windows Host network or with the OPAL-RT Simulator.
Two OP8331 splitter cables, at least. A complete setup for all I/O’s on both slots will require eight cables.
One DB37 gender changers or cable, at least. A complete setup for all I/O’s on both slots will require six cables.
OP48XX Expansion Chassis
Connect the OP48XX chassis to a real-time simulator using the PCIe cable.
Connect the OPAL-RT simulator to the same network as the host using an Ethernet cable.
Connect the OP48XX chassis to the network, or to a local network with the OPAL-RT simulator, using an Ethernet cable.
An OP48XX chassis has two H-factor mezzanine module slots. For this example, both slots should have an OP48H30 I/O Module installed.
To set up I/O’s loop-backs, you will need to connect an OP8331 splitter cable to each targeted module slot connector.
OP48H30 Slot Connectors | OP8331 Splitter Cable Connectors |
|---|---|
P1 (Ain Ch. 00-15 / Aout Ch. 00-15) | P1-B1 (Ain Ch. 00-15) |
P1-B2 (Aout Ch. 00-15) | |
P2 (Dio Ch. 00-31) | P2-B1 (Dio Ch. 00-15) |
P2-B2 (Dio Ch. 16-31) | |
P3 (Aout Ch. 16-47) | P3-B1 (Aout Ch. 16-31) |
P3-B2 (Aout Ch. 32-47) | |
P4 (Dio Ch. 32-63) | P4-B1 (Dio Ch. 32-47) |
P4-B2 (Dio Ch. 48-63) |
OP48H30 I/O's Loop-backs
Each OP48H30 module supports 48 analog outputs but only 16 analog inputs. So there are three ways to set up an analog loop-back, depending on the analog outputs range targeted:
For analog outputs, range 00-15: connect between P1-B2 and P1-B1.
For analog outputs, range 16-31: connect between P3-B1 and P1-B1.
For analog outputs, range 32-47: connect between P3-B2 and P1-B1.
Each OP48H30 module also supports 64 configurable digital I/Os.
For Static digital I/O’s: connect between P4-B1 and P2-B1.
For PWM or TSD digital I/O’s: connect between P4-B2 and P2-B2.
I/O Interface Configuration
All OPAL-RT Board configurations are performed via HYPERSIM's GUI, under the “I/O Interface” section of the project.
Before starting the simulation, configure the following chassis information:
Chassis type: Only
OP4810 (Versal)orOP4815 (Versal)are supported.IP address and Chassis ID: Available on the OP48XX chassis LCD screen.
(Optional) Chassis name: Displayed on the OP48XX chassis LCD screen.
You can also get this information by running the flashupdate -enumRemote command in an SSH session on the OPAL-RT real-time simulator.
flashupdate command
Simulation and Results
The example model includes designs for each I/O type supported by the OP48H30 modules:
Analog I/Os
Static Digital I/Os
Pulse Width Modulated I/Os
Time-Sampled Digital I/Os
For more details about the OPAL-RT Board configuration, please refer to the OPAL-RT Board I/O Interface documentation.
After the simulation is started, Inputs and Outputs signals can be inspected and compared using the ScopeView tool. A predefined template file named OP40810_OP4815_Integration_OP48H30.svt is available in the example project directory.
Analog I/O’s
Each OP48H30 module has eight groups of eight analog I/O channels:
Two groups are analog inputs:
Ain Channels 0-7 (connector P1)
Ain channels 8-15 (connector P1)
Six groups are analog outputs:
Aout channel 0-7 (connector P1)
Aout channels 8-15 (connector P1)
Aout channels 16-23 (connector P3)
Aout channels 24-31 (connector P3)
Aout channels 32-39 (connector P3)
Aout channels 40-47 (connector P3)
This example model defines eight reference analog signals that are sent to all groups of analog outputs in both slots, supporting any of the analog loop-back configurations.
The ScopeView pages AIO1 and AIO2 display the 16 analog inputs for each slot. Each graph shows one analog input and its associated reference analog output.
Static Digital I/O’s
Each OP48H30 module has eight groups of eight configurable digital I/O channels. Four of these groups are configured as static digital I/Os:
Dio channels 0-7: static digital inputs (connector P2)
Dio channels 8-15: static digital inputs (connector P2)
Dio channels 32-39: static digital outputs (connector P4)
Dio channels 40-47: static digital outputs (connector P4)
This example model defines eight random binary reference signals that are sent to all groups of static digital outputs in both slots.
The ScopeView pages DIO1 and DIO2 display all static digital inputs, from channels 0 to 15. Each graph shows one static digital input and its associated reference random binary output.
Pulse Width Modulated I/O’s
Each OP48H30 module has eight groups of eight configurable digital I/O channels. Two of these groups are configured as Pulse Width Modulated I/Os:
Dio channels 16-23: PWM digital inputs (connector P2)
Dio channels 48-55: PWM digital outputs (connector P4)
This example model defines eight frequencies (from 100 Hz to 800 Hz) and eight duty cycle ratios (from 0.1 to 0.8) that are sent to the PWM digital output group of each slot.
The ScopeView pages PWMIO1 and PWMIO2 display the eight frequencies and the eight duty cycle ratios detected from the PWM digital input channels. Each graph shows the frequency or duty cycle ratio detected for an input channel and the associated reference value.
Time Sampled Digital I/O’s
Each OP48H30 module has eight groups of eight configurable digital I/O channels. Two of these groups are configured as Time-Sampled Digital I/Os:
Dio channels 24-31: TSD Event Detector (connector P2)
Dio channels 56-63: TSD Event Generator (connector P4)
This example model defines eight reference sequences of events. Each sequence contains four events (rising, falling, rising, falling) at different ratio values.
The ScopeView pages TSDIO1 and TSDIO2 display, side by side, the four ratio values of the events generated by an output channel and the ratio values of the events detected on the associated input channel. The types of events (rising or falling edges) are not shown.