Example | OP4810-IO/OP4815-IO with OP48H10

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Example | OP4810-IO/OP4815-IO with OP48H10

Page Contents


Location

This example model is available in the software under the “IO Interfaces” category, with the file name: OP4810_OP4815_Generic_Integration.ecf.

Description

This example project demonstrates how to use the OPAL-RT Board interface to interact with Analog, Static Digital, and Pulse Width Modulation (PWM) signals provided by an OP48XX-IO FPGA expansion chassis, such as the OP4810-IO or OP4815-IO. For this example, a OP48H10 Fast I/O type H Module must be installed in slot 1 of the FPGA expansion chassis.

More information can be found in the Hardware Products Documentation about OPAL-RT hardware products:

To execute this example project, you will need:

  • One OPAL-RT Simulator, that supports I/O expansion chassis.

  • One OP48XX expansion chassis, with a OP48H10 in slot 1.

  • One PCIe cable, between the OPAL-RT Simulator and the OP48XX expansion chassis.

  • Two Ethernet cables:

    • One between the OPAL-RT Simulator and the Windows Host network.

    • One between the OP48XX expansion chassis and the Windows Host network or with the OPAL-RT Simulator.

  • Two DB37 loop back cables.

OP48XX-IO Expansion Chassis

  • Connect the OP48XX-IO chassis to a real-time simulator using the PCIe cable.

  • Connect the OPAL-RT simulator to the same network as the host using an Ethernet cable.

  • Connect the OP48XX-IO chassis to the network, or to a local network with the OPAL-RT simulator, using an Ethernet cable.

  • An OP48XX chassis has two H-factor mezzanine module slots. For this example, slot 1 should have an OP48H10 I/O Module installed.

SimulatorExpansionUnitWirering.png
Example Hardware Setup

 

OP48H10 Module Loop Backs

The OP48H10 module supports 16 analog outputs, 16 analog inputs and 32 configurable digital I/Os. Digital and analog loop backs are used in the example model to test the functionality of the system.

  • For digital I/O’s: connect between P1 and P2 of slot 1.

  • For analog outputs: connect between P3 and P4 of slot 1.

I/O Interface Configuration

All OPAL-RT Board configurations are performed via HYPERSIM's GUI, under the “I/O Interface” section of the project.

IO Interface Configuration.png
I/O Interface Configuration

Before starting the simulation, configure the following chassis information:

  • Chassis type: Only OP4810 (Versal) or OP4815 (Versal) are supported.

  • IP address and Chassis ID: Available on the OP48XX chassis LCD screen.

  • (Optional) Chassis name: Displayed on the OP48XX chassis LCD screen.

OP4815-LCD_screen.jpg
Use the menu button to display chassis information on LCD screen

You can also get this information by running the flashupdate -enumRemote command in an SSH session on the OPAL-RT real-time simulator.

root@rtserver:/usr/opalrt/common# /usr/opalrt/common/bin/flashupdate -enumRemote =================================================================== OPAL-RT FLASH UPDATE PROGRAM V2.6 OPAL-RT FLASH UPDATE RT-LAB path is /usr/opalrt/v2025.1.3.77 OPAL-RT TECHNOLOGIES INC. All rights reserved, Copyright 2015. Compiled on Mar 28 2025 ----- CENTRAL BOARD ----- VM1X02 board found (VendorID=0x1B2C, DeviceID=0x1402) PCI Index: 0 IRQ Number: 11 RT-XSG: 3.7.2.2 Chassis ID: 0 Card type: VM1X02_1402_5R Bus type: EX Minor ID: 1 Revision ID: 4 Speed 5GT/s Width x4 ARM Core: Software version: 1.3.0 Ethernet 1: MAC address: 54:91:AF:00:00:53 IP: 192.168.3.5 (Reachable) Netmask: 255.255.255.0 Gateway: 192.168.3.1 OPAL-RT Board: VM1X02 boards search done. OPAL-RT Board: XDMA registers mapped successfully. XDMA engine succesfully configured in Versal board with board index 0. PCIe detection of VM1X02 cards: XDMA engine succesfully configured in Versal board with board index 0.
flashupdate.png
Chassis information from flashupdate command

 

Simulation and Results

The example model includes designs for different I/O type supported by the OP48H10 modules:

  • Analog I/Os

  • Static Digital I/Os

  • Pulse Width Modulated I/Os

OP48XX-IO Example Model.png
OP48XX-IO Example Model

After the simulation is started, Inputs and Outputs signals can be inspected and compared using the ScopeView tool. A predefined template file named OP40810_OP4815_Generic_Integration.svt is available in the example project directory.

image-20251124-203559.png
ScopeView Predefined Template File

Analog I/O’s

Each OP48H10 module has 4 banks of eight analog I/O channels:

Two banks are analog outputs:

  1. Aout channel 0-7 (connector P3)

  2. Aout channels 8-15 (connector P3)

Two banks are analog inputs:

  1. Ain Channels 0-7 (connector P4)

  2. Ain channels 8-15 (connector P4)

image-20251124-204447.png
Analog I/O’s Configuration

This example model defines sixteen reference analog signals that are sent to the two analog output banks.

image-20251125-161929.png
Analog I/O’s model

The ScopeView page AIO displays the 16 analog inputs for slot 1. Each graph shows one analog input and its associated reference analog output.

Analog.png
Analog IO’s ScopeView

Static Digital I/O’s

The OP48H30 module has four banks of eight configurable digital I/O channels. Two of these banks are configured as static digital I/Os:

  1. Dio channels 0-7: static digital inputs (connector P1)

  2. Dio channels 16-23: static digital outputs (connector P2)

image-20251125-162259.png
Static digital I/O’s configuration

This example model defines eight random binary reference signals that are sent into the static digital output bank.

image-20251125-161823.png
Static digital I/O’s model

The ScopeView page DIO displays all static digital inputs, from channels 0 to 7. Each graph shows one static digital input and its associated reference random binary output.

Digital.png
Static Digital I/O’s ScopeView

Pulse Width Modulated I/O’s

The OP48H30 module has four banks of eight configurable digital I/O channels. Two of these groups are configured as Pulse Width Modulated I/Os:

  1. Dio channels 8-15: PWM digital inputs (connector P1)

  2. Dio channels 24-31: PWM digital outputs (connector P2)

image-20251125-163321.png
PWM I/O’s configuration

This example model defines eight frequencies (from 100 Hz to 800 Hz) and eight duty cycle ratios (from 0.1 to 0.8) that are sent to the PWM digital output bank.

image-20251125-163619.png
PWM I/O’s model

The ScopeView page PWM displays the eight frequencies and the eight duty cycle ratios detected from the PWM digital input channels. Each graph shows the frequency or duty cycle ratio detected for an input channel and the associated reference value.

PWM.png
PWM I/O’s ScopeView