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Location

This example model can be found in the software under the category "Transmission" with the file name "FPGA-BASED_Frequency_Dependent_Line.ecf".

Description

This model illustrates how to use the frequency-dependent line (FD Line) developed in schematic editor software and solved using the eHS solver. It represents the true nature of a transmission line by modeling the line parameters as distributed and frequency-dependent. The line resistance and inductance are evaluated as functions of frequency. In this example model, the FD line used has 3 phases. This example is based on OPAL-RT's real-time simulator utilizing the FPGA to simulate the behavior of a frequency-dependent line in real time. One HYPERSIM model and one Schematic Editor model are provided to illustrate the exchange of information between the controller and plant. The minimum/maximum length of the line is dependent on the eHS sampling time.

The model represents a 150km three-phase frequency-dependent line with three-phase voltage sources at both ends. The phase of the left and right voltage sources can be controlled via the phase block in the console. Three controllable faults to the ground are placed at different points on phase A of the line. One at 75km, one at 100km, and one at 125km. The fault location is configurable via the FaultLocation constant. Voltage and current measurements are placed at the beginning, end and each fault location along the line for each phase.

Requirements

The HYPERSIM, Schematic Editor/Unified Database, and eFPGASIM toolboxes must be installed on the host and target computers to run this example model properly. Please refer to the product documentation for details on version compatibility. Also, the minimal time step in this example is 20µs.

Setup and Connections

For this example model, HYPERSIM Model, Schematic Editor, and I/Os need to be configured.

HYPERSIM Model Configurations

For each FD line, upload your parameters from the .pun files

Select fault Location using Fault Location constant

Schematic Editor Configurations

In Schematic Editor, the target needs to be properly set:

1. Click on your firmware configuration at the bottom left of Schematic Editor.

2. Select or create your simulation setup. Your FPGA Firmware should support the FD Line model.
   
   

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3. Click on the Solver Settings button next to your firmware configuration button.

4. Define your solver settings for the simulation.

The example model in HYPERSIM is reproduced in Schematic Editor. See the figure below.

The faults are produced using Rfault resistors (Rfault1, Rfault2, and Rfault3) and values are set depending on the FaultLocation in the HYPERSIM model.

IO Configuration

Since part of the simulation is done through eHS, it is required to connect HYPERSIM to it. Here are the steps for that configuration:

1. Open the I/O Interface Configuration

2. Add an OPAL-RT Board
   
   

    

3. Select the correct Chassis ID. This example uses an OP5707 (Virtex-7) target.

4. Select Optical for the type of generated synchronization signal.

5. Select Standard repositories for the bitstream configuration location, then select your bitstream configuration file. In this example, the bitstream configuration file is
   VC707_2-EX-0001-eHSx128_Gen4_PowerSystems_FDLine_IOConfig1.opal
   And the bitstream name is
   VC707_2-EX-0001-3_4_0_814-eHSx128_Gen4_PowerSystems_FDLine_IOConfig1-2C-02.bin

Simulation and Results

The simulation has been executed and results with a fault at location 1 (at 75 km from the left source) have been recorded. The two figures below presents respectively currents I1, I2, I3, I4 and I5 and voltages V1, V2, V3, V4, and V5 on eHS. The system remains balanced in a steady state before the fault occurs in phase A. At t = 0.15 s, the harmonic content on voltage and current increases due to the fault.

In the figures below, the focus is on the comparison of results obtained in HYPERSIM vs eHS. The system remains balanced in a steady state before the fault occurs on phase A at t = 0.1s. The fault is propagated on the line and is measured by eHS in blue at t = 0.1s. on phase A. At t = 0.15 s, the harmonic content on voltage and current increases due to the fault, but eHS has the computational capacity to better show the harmonic content in current and voltage through the line. The following figures show results of current and voltage on the first bus phase A on a real-time simulation performed at a time step of 20 µs in real-time on HYPERSIM (red curves) and a time step of 1 µs on eHS (blue curves).

In this zoomed figure at t = 0.15s, it is observed the harmonic content is higher in eHS than the one observed in HYPERSIM due to the different time step of simulation.

VTo compare results with the same time step on both eHS and HYPERSIM, results were recorded in eHS with a time step of 1 µs and then the same simulation was executed offline in HYPERSIM at also a time step of 1 µs. The results in the figure below show the similarities in results from HYPERSIM and eHS at the same time step.