V2.20 Versal OP4810 - eHS x128 - Gen5 - PMSM - IO Config2

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V2.20 Versal OP4810 - eHS x128 - Gen5 - PMSM - IO Config2

OPAL-RT TECHNOLOGIES
1751 Richardson suite 1060, Montréal QC Canada H3K 1G6
www.opal-rt.com

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SPS workflowSCHEMATIC EDITOR WORKFLOWSCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

Introduction

This firmware includes:

  • One eHS x128 Gen5 Solver

  • One Dual Permanent Magnet Synchronous Machines (PMSM VDQ) models

  • Two Analog Output Mapping and Rescaling (AOMR) module

  • Two Analog Input Differential Rescaling (AIR) module

 

LoadIn/DataIn/DataOut mapping

 

LoadIn

DataIn

DataOut

1

Config eHS

Inputs eHS

eHS Averaged

2

Scenario / Rst eHS = Status

TSDO 1 - eHS 0 to 7

eHS DownSample

3

 

TSDO 2 - eHS 8 to 15

Digital In 1A - 0 to 7

4

PWM 1A -  0 to 7

TSDO 3 - eHS 16 to 23

Digital In 1A - 8 to 15

5

PWM 1A -  8 to 15

TSDO 4 - eHS 24 to 31

Digital In 2A - 0 to 7

6

 

TSDO 5 - eHS 32 to 39

Digital In 2A - 8 to 15

7

 

TSDO 6 - eHS 40 to 47

Analog In 2D - 0 to 7

8

PWM 2A -  0 to 7

TSDO 7 - eHS 48 to 55

Analog In 1D - 0 to 7

9

PWM 2A -  8 to 15

TSDO 8 - eHS 56 to 63

PMSM VDQ 1/2

10

 

TSDO 9 - eHS 64 to 71

QEI 0

11

 

Digital Out 1A - SDO 0 to 7

QEI 1

12

 

Digital Out 1A - SDO 8 to 15

RMS and Power calculation

13

eHS PWM 1 - eHS 0 to 7

 

eHS Period Averaged

14

eHS PWM 2 - eHS 8 to 15

 

eHS Period DownSample

15

eHS PWM 3 - eHS 16 to 23

Digital Out 2A - SDO 0 to 7

TimeOn Averaged

16

eHS PWM 4 - eHS 24 to 31

Digital Out 2A - SDO 8 to 15

TimeOn DownSample

17

Config AIR

 

 

18

Config PMSM SH 1/2

 

 

19

 

AOMR/Analog Out 1A 0 to 7

 

20

 

Analog Out 1A 8 to 15

 

21

Config QEI 0

Analog Out 1A 16 to 24

 

22

Config QEI 1

Analog Out 2A 16 to 24

 

23

Config SFP

eHS PWM 1 -  0 to 7

 

24

Config LUT

eHS PWM 2 -  8 to 15

 

25

Config RMS

eHS PWM 3 -  16 to 23

 

26

Config QEO

eHS PWM 4 -  24 to 31

 

27

 

eHS SWG

 

28

 

PMSM VDQ 1/2

 

29

 

 

 

30

 

SFP

 

31

 

AOMR/Analog Out 2A 0 to 7

 

32

 

Analog Out 2A 8 to 15

 

33

 

QEO

 

34

 

TSDO 10 - eHS 72 to 79

 

35

 

TSDO 11 - eHS 80 to 87

 

36

 

TSDO 12 - eHS 88 to 95

 

37

 

TSDO 13 - eHS 96 to 103

 

38

 

TSDO 14 - eHS 104 to 111

 

39

 

TSDO 15 - eHS 112 to 119

 

40

 

TSDO 16 - eHS 120 to 127

 

41

 

TSDO 17 - eHS 128 to 135

 

42

 

TSDO 18 - eHS 136 to 143

 

43

 

LUT

 

System Overview

 

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Permanent Magnet Synchronous Machine models (PMSM VDQ)

A total of two PMSM motors are available and configured using the Permanent Magent Synchronous Machine. The machine type could be Constant DQ, Variable DQ or BLDC. 


Schematic Editor Workflow - PMSM (VDQ - BLDC) block

Communication port configuration for the Dual PMSM (VDQ) block

      

Dual PMSM Motors VDQ

Machine Label

PMSM 1

PMSM 2

Data In Port Number

28

Load In Port Number

18

Data Out Port Number

9

Connectivity (Input)

The signals received could be used as external carrier for machine resolver module. 
Analog In - Slot 1D - Ch00-07 Analog In - Slot 2D - Ch00-07

Encoder Output

Encoder outputs are sent to 
Digital Out - Slot 1B Digital Out - Slot 3B

Hardware Pin assignment

 

Encoder 1

Encoder 2

 

Encoder 1

Encoder 2

A

Ch00

Ch04

B

Ch01

Ch05

Z

Ch02

Ch06

 

Power calculation module

SPS WORKFLOW SPECIFIC SCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

RMS and power calculation for all circuit measurements is configured using the “Power Measurement Controller” block in the CPU model.

 

For more documentation on the block see : https://opal-rt.atlassian.net/wiki/spaces/PFPET/pages/65835684/CPU+Power+Measurement+Configuration+-+efs+Monitoring+cpuPowerBlock

 

Communication port configuration for the Power calculation block

 

RMS

 

RMS

Load In Port Number

25

Data Out Port Number

12


Analog Output Mapping and Rescaling module (AOMR)

AUTOMATIC AND NOT VISIBLE IN SCHEMATIC EDITOR WORKFLOW

There is one AOMR block allowing to configure all 32 analog outputs.

AOMR Master Subsystem (SM) block

Communication port configuration for the Analog Output Mapping and Rescaling (AOMR) block

 

AOMR - Slot 1C

AOMR - Slot 2C

 

AOMR - Slot 1C

AOMR - Slot 2C

Version 

V2

Data In Port Number

19

31

Load In Port Number

12

20

AOMR Output

Lane Index

Signal Source

Details

Lane Index

Signal Source

Details

0

eHS Outputs

eHS Y01-128

1

PMSM VdQ 1/2 AnalogOut

2

Data Stream from SFP #01

 


SFP Mapping and Communication Block

A total of 32 inputs and 32 outputs are available and configured using the SFP mapping and communication block.

Schematic Editor Workflow - SFP Mapping and Communication block


Communication port configuration for the SFP mapping and communication block

 

SFP - Channel 4

 

SFP - Channel 4

Data In Port Number

30

Load In Port Number

23


Analog In module (AI)

AI block reads signals from analog input channels on the simulator. 

Communication port configuration for the Analog Input (AI) block

 

Slot 1C

 

Slot 1C

Channels

Ch00-07

Data Out Port Number

8

 

Slot 2C 

 

Slot 2C 

Channels

Ch00-07

Data Out Port Number

7

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


 

Communication port configuration for the Analog Output (AO) block

 

Slot 1C

Slot 2C

 

Slot 1C

Slot 2C

Channels

Ch00-07

Ch08-15

Ch16-23

Ch00-07

Ch08-15

Ch16-23

Data In Port Number

19

20

21

31

32

22

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


 

Communication port configuration for theDigital Input (DI) block

 

Slot 1A 

Slot 2A

 

Slot 1A 

Slot 2A

Channels

Ch00-07

Ch08-15

Ch00-07

Ch08-15

Data Out Port Number

3

4

5

6

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


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