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SCHEMATIC EDITOR

Table of Contents

• 1 Block
• 2 Description
• 3 Mask
• 4 Inputs
• 5 Outputs
• 6 Characteristics and limitations

Description

This block implements a signal mapping and rescaling interface to control analog output channels according to signals originating from the RT-XSG (FPGA) or RT-LAB (CPU) model. The signal mapping as well as the gain, offset, minimum and maximum are configured from the Schematic Editor. The gain and offset can be configured dynamically during simulation, by connecting a CPU input to the needed parameter via the Schematic Editor. See the image below for an example.

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This block is capable to map from up to eight serial input in the OPAL-RT FLWS Protocol format to up to 64 analog output channels.

Mask

Number of Serial Signals: This is used to specify the number of serial signals that will appear at the input of the block. That is, if we set X serial signals in the mask, we will have X “Model Signal Serial” inputs to the block. The role of these inputs are described in the Inputs section.

Enable channel by channel naming: This is used to toggle between the “channel sources” view (when unchecked) and the “channel by channel naming” view (when checked).

Channel sources view:

This view allows the user to select predefined mapping options based on the selected hardware. Different views are showed for different OPAL Hardware platforms (7series, Versal, OP4300, etc) with all different views minimizing the need for manual input from the user. Essentially, the view for

• 7 series: Allows the user to select to which IO slot (1A, 1B, 2A, … 4B) to map each 4 groups of 16 analog channels.

• Versal: Allows the user to select which Type H IO card is connected to Slot 1 and Slot 2

• OP4300: Has no selectable mapping input, all Analog Output channels are mapped to Port P4 on the chassis.

Channel by channel naming view:

• Number of configured channels: This allows the user to select an amount of channels that will be configured by this block. Must be an integer in the range [1, 64]. The textboxes used to name the channels will dynamically be enabled/disabled so that only the first X are enabled, where X is the value entered here.

• Ch {1..64}: This allows the user to set the name of each channel. Duplicate names are not allowed, and will cause an error on an “Update Diagram” action.

Inputs

Sync: This input must be a Bool or UFix1_0 signal. It should be a pulse train whose period is equal to the sample time requested for the Analog Output channels. Refer to the Hardware documentation for the minimum sampling time of the interface.

DataIn: This input should be connected to the solver's Data In configuration port.

DataInSof: This input should be connected to the solver's Data In configuration start of frame port.

LoadIn: This input should be connected to the solver's Load In configuration port.

LoadInSof: This input should be connected to the solver's Load In configuration start of frame port.

Model Signal Serial {1..8}: These inputs are providing the FPGA signals that could be mapped to the analog output channels. They have to follow the OPAL-RT FLWS Protocol. Inner data size is 32 bits (i.e XFloat8_24), any additional bit would be discarded. Each input can transport a maximum of 128 channels. As an example, this signal could be provided by eHS solver. (Gen4 onwards).

Outputs

high speed FLWS: This bus output returns the values of the 64 output channels in XFloat8_24 output data following the OPAL-RT FLWS Protocol. Thus, it is a bus output that includes a Data, Valid and Last signal. This output is oversampled, to the same speed as the oversampling clock specified in the RT-XSG Synthesis Manager,

FLWS: This bus output returns the values of the 64 output channels in XFloat8_24 format, following the OPAL-RT FLWS Protocol. Thus, it is a bus output that includes a Data, Valid and Last signal. This output is downsampled to the primary clock frequency.

Configured SLOT_N: This output returns the state of the corresponding slot selected in the block dialog, whether it is configured or not. If this slot is configured by receiving Data on its Load In signal that is to be sent to it, the Configured port outputs 1. If not, the Configured port outputs 0. Note that this output does not appear if the corresponding slot is set to "unconnected."

Out: This bus output contains the following signals

• ch15_ch00

  • conv: This output is conversion command that should be connected to the first Analog Output I/O interface.

  • ch{0..15}: These outputs are the 16 mapped and rescaled channels that should be connected to the first Analog Output I/O interface. The output format is Fix16_11 in the case of 7-series FPGA, and XFloat8_24 for Versal-series FPGA.

• ch31_ch16

  • conv: This output is conversion command that should be connected to the second Analog Output I/O interface.

  • ch{16..31}: These outputs are the 16 mapped and rescaled channels that should be connected to the second Analog Output I/O interface. The output format is Fix16_11 in the case of 7-series FPGA, and XFloat8_24 for Versal-series FPGA.

• ch47_ch32

  • conv: This output is conversion command that should be connected to the third Analog Output I/O interface.

  • ch{32..47}: These outputs are the 16 mapped and rescaled channels that should be connected to the third Analog Output I/O interface. The output format is Fix16_11 in the case of 7-series FPGA, and XFloat8_24 for Versal-series FPGA.

• ch63_ch48

  • conv: This output is conversion command that should be connected to the fourth Analog Output I/O interface.

  • ch{48..63}: These outputs are the 16 mapped and rescaled channels that should be connected to the fourth Analog Output I/O interface. The output format is Fix16_11 in the case of 7-series FPGA, and XFloat8_24 for Versal-series FPGA.

Characteristics and limitations

When being used with targets equipped with 7 series FPGAs (Virtex7, Kintex7), this block can only be connected to analog output interfaces that accept the Fix16_11 fixed-point format for their inputs, and to other blocks (for example, a Machine add-on) that accept FLWS inputs (which can be connected to one of this block’s FLWS outputs).

The core of this block runs at the same speed as the oversampling clock specified in the RT-XSG Synthesis Manager. Thus, when using this block, it is very important to choose the proper clock while configuring the bitstream generation.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/ .