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SFP Mapping and Communication Block - efs_sfp_mapping_communication
Description
This block implements a signal mapping and rescaling interface to send up to 32 SFP signals from 8 FLWS model serial signal links and 1 Data In link from the CPU.
The transfer can be triggered by either an internal synchronization signal, or any of the 8 input FLWS links last signal.
It also receive data from the SFP channel associated to it.
Mask
SFP Channel Number Selection: This parameter is to select the SFP channel that this block will use.
Inputs
LoadIn, LoadInSof: This loadin port is to receive mapping, gain, offset and synchronisation configuration from CPU.
DataIn, DataInSof: This datain port is used for transfering real time channels from the CPU.
Model Signal Serial {1..8}: These inputs are providing the FPGA signals that could be mapped to the SFP output channels. They have to follow the OPAL-RT FLWS Protocol. Inner data size is 32 bits (i.e XFloat8_24), any additional bit would be discarded. Each input can transport a maximum of 128 channels. As an example, this signal could be provided by the eHS (Gen4 onwards) or a machine model. The SFP channels transfer can be triggered by any of these input links by using the right Synchronisation source configuration from the LoadIn port.
Outputs
toEhs: This output has FLWS signal received from the associated SFP link. This should be connected to a eHS external input port.
Characteristics and limitations
Direct Feedthrough | NO |
Discrete sample time | YES |
XHP support | N/A |
Work offline | NO |
If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.
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