Description

This block implements PID controller on FPGA, using the backward-Euler technique. Both input and outputs are in single floating-point format, and the internal state variable is in double floating-point format.

Mask Parameters

Use external synchronization source: When this option is selected, an input port for the sample time synchronization will be available. The external synchronization will have to be a pulse train with the same period as the sample time of the controller.

Inputs

s(n): This input must be a XFloat8_24 signal. It is the controlled signal to be compared with a reference.

reset: This input must be a UFix1_0 signal. When active, the integrator state variable is reset to its initial condition.

s_ref: This input must be a XFloat8_24 signal. It is the reference value for the input signal of the controller.

Params: This input must be connected to the PID Control Unpacking block. It contains the controller parameters as set from the PI control block located in the RT-LAB simulation model.

Sync: This input must be a UFix1_0 signal. It is available only if the "Use external synchronization source" option is selected, and must be a pulse train with a period equal to the controller sample time, as set in the PID control block located in the RT-LAB simulation model.

Outputs

y(n): This output is the control variable, and is in single floating-point numerical format (XFloat8_24).

Characteristics and limitations

Direct Feedthrough	NO
Discrete sample time	YES
XHP support	N/A
Work offline	YES

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.

Block

Description

Mask Parameters

Inputs

Outputs

Characteristics and limitations

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