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Using eHS with Schematic Editor
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Using eHS with Schematic Editor
- Sylvain Ménard
Owned by Sylvain Ménard
Last updated: Mar 07, 2023
This page focuses on our main workflow based on our brand new Schematic Editor.
- Quick start guide : Run a model on FPGA using the Schematic Editor
- Block Library
- Schematic Editor Block Library
- SPS Block Library
- eHS Variable Load
- Generic Machines
- Resolver Encoder Sensors
- Variable Load Parameter
- Variable Load Configurator
- 24-Phase H-Bridge Inverter
- 24-Phase Hysteresis Controller
- 24-Phase Permanent-Magnet Synchronous Machine
- Analog Input Differential Rescaling Controller
- Analog Out Mapping Rescaling V2 Control Panel
- Chassis Selection
- Analog Out Mapping and Adjustments
- CPU stubline configuration
- Digital Output Mapping
- Dual Angle Sensors with faults CPU
- Dual eHS SPS
- Dual PMSM Motors SH v1
- Dual PMSM Motors SH Advanced Command
- Dual PMSM Motors SH v2
- Dual PMSM Motors VDQ Advanced Command
- Dual PMSM Motors VDQ
- Dual Vabc Test Sources Block
- eHS Data Convert for SFP
- eHS Gen3 SPS DEPRECATED
- eHS Offline simulation
- eHS Solver License Class
- eHSx32 for OP4200
- eHSx64 Command block
- Foster thermal network
- FPGA 2 inputs dot product configuration block
- FPGA 64-to-64 Interconnect Controller Block
- FPGA 64-to-64 Interconnect Controller Panel
- FPGA Discrete 1-Phase PLL
- FPGA First-Order Filter
- FPGA PI Controller
- FPGA PID Controller
- FPGA Second-Order Filter
- Generic High Speed Communication Block for eHS
- Generic Machines Induction Machine Model
- Generic Machines Permanent Magnet Synchronous Machine PMSM Model
- Generic Machines Synchronous Machine Model
- Induction Machine Command
- Inverter Solver with Boost Command
- Left side / Right side stubline
- Resolver Encoder Mapping
- RT-XSG Scope Series
- RT-XSG Scope Series Control
- Selectable Digital Input
- Selectable Digital Output
- Machine Interface Parallel to Parallel and Serial to Parallel Wrapper
- Solver Time Step Counter
- Switched-Reluctance Motor
- Switched Reluctance Motor Hysteresis Controller
- Switching function configuration
- Thermal losses feature
- Time-multiplexed Capacitor Differential Equation Solver Configuration
- Vabc Test Source
- eHS Frequency dependent line block
- Parallel to Parallel Interface
- Serial to Parallel Interface
- Conf File writing Conventions
- eHS Gen4 SPS
- Half Line
- CPU Power Measurement Configuration
- Analog Out Mapping Rescaling V1 Control Panel
- XSG Block library
- Analog Output Mapping and Rescaling Block V2
- FLWS Filter
- 1D-LookUp Table for XSG
- Variable state space block
- SFP Mapping and Communication Block
- FLWS Mapping and Rescaling Block
- Analog Output Mapping and Rescaling Block V2
- Angle Sensor Emulator block
- Capacitor Differential Equation Solver
- Digital Output Mapping
- Discrete 1-Phase PLL
- Discrete First-Order Filter Single floating-point
- Discrete Second-Order Filter
- Dual PMSM Model
- Dual PMSM SH Solver block
- Dual PMSM VDQ Solver block
- Dual Resolver Encoder
- eHS solver for RT-XSG block
- eHS Gen3 solver for RT-XSG block
- eHS to Machines Mapping Interface
- FPGA 64-to-64 Interconnect Block
- Analog Output Mapping and Rescaling Block
- Analog Input Differential Rescaling Block
- eHS Gen3s Solver for XSG
- eHS Gen4 Solver for XSG
- Frame-based LightWeight Serial FLWS Protocol for RT-XSG models
- Frequency dependent line
- Generic Machines block
- Induction Machine Solver block
- Initialization Bus Address Filter
- Initialization Bus Data ID filter
- Initialization Bus Param ID filter
- Initialization Bus Ram Interface
- Initialization Decoder
- Integrator Block
- Machine to eHS Interface 4x and 8x
- Mechanical Model Block
- Parallel to Parallel Interface block
- PI Controller block
- PID Controller block
- Resolver Encoder block
- Route Mechanical Signals block
- RT-XSG Scope Block
- RT-XSG Scope Series Block
- Saturable transformer
- Selectable Digital Input
- Selectable Digital Output
- Serial to Parallel Interface block
- Switched Reluctance Machine Solver block
- Time-multiplexed Capacitor Differential Equation Solver
- XSG thermal losses block
- Custom Model XSG
- eHS Gen5 Solver for XSG
- Induction Machine With Saturation block
- SFP Data Type Convert for FLWS
- FPGA Power Measurement
- FPGA Min Max Measurement Block
- Digital Input Mapping Block
- Block Library
- Quick start guide : Update a model on FPGA using the Schematic Editor
- User Notifications from FPGA Power Electronic Toolbox
- How to integrate eHS Block
- FPGA-based Power Electronics Toolbox Produced Content
- How to tune eHS solver specific parameters
- eHS Gen4 solver
- eHS Gen5 solver
- How to choose discretization Method (Pade5 and Backward Euler)
- How to choose Solver Strategy (Smallest Time Step vs Lowest Latency)
- How to choose switch model (Pejovic and Quasi-supra)
- How to achieve accurate results with switching components using interpolation
- How to tune single switch parameters (Rdamp and Relax)
- How to tune two- and three-level switches (Prediction and Relaxation)
- How to integrate a firmware containing external models in the Schematic Editor
- How to tune machine snubbers
- eFPGASIM with RT-XSG Module - Rules and recommendations
- How to connect digital signals to eHS Gating Inputs with Schematic Editor
- How to create FPGA-based Custom Model compatible with Schematic Editor workflow
- How-to decouple eHS Gen5 circuit to improve minimum time step
- Discrepancies between single switches
- How to configure a generalized mutual inductance
, multiple selections available,
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