Description

This block implements a rescaling interface intended to get signals from an analog input interface. Its inputs are fixed-point Fix16_10 signals and the rescaled outputs are made available in Singla floating-point format.

Mask Parameters

Provide parallel outputs (composite signal): This option, when selected, creates an output to the block for parallel access to all outputs.

Provide serial outputs (stream): This option, when selected, creates an output to the block for serial access to all outputs.

Inputs

Sync: This input must be a Bool or UFix1_0 signal. It triggers the rescaling function.

Ch01_Ch00 .. Ch15_Ch14: Each of these inputs accepts one signals on which two Fix16_10 channels are concatenated. Even-numbered channels occupy the 16 least-significant bits (LSBs) of each input and odd-numbered channels occupy the following 16 bits. Any remaining bits after these 32 LSBs are disregarded, for an easy connection to the 33-bit outputs of the RT-XSG I/O block controlling the analog input interface.

Configuration: This input should be a bus containing all the rescaling function parameters. It should be connected to a "Analog Input Defferential Rescaling Unpacking" block.

Outputs

Scaled signals (parallel): This output is a composite signal containing 16 sub-signals corresponding to the rescaled inputs, in the single floating-point format (Xfloat8_24). Signal names are ch0 through ch15.

Scaled signals (serial): This output provides serially streamed Analog Input Differential Rescaling Block's outputs for use in the RT-XSG model. It is provided as a Bus following the OPAL-RT FLWS protocol. This output contain a stream of signals, in which the LSB is a "Last data" flag, the following bit is a "Data valid" flag and the remaining bits are the 16 channels in Xfloat8_34 extended single floating-point numerical format, sent serially and in order from channel 0 through 15, and synchronously with the "Data valid" flag. This output is intended for direct connection to a FPGA-based solver getting its inputs serially, such as the eHS solver.

Characteristics and limitations

Because of the pipelined implementation of the rescaling function, the Sync pulse train should have a minimum period of 17 clock cycles.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.