Location

This example model can be found in the software MMC under the directory of /Examples/MMC_cpu_HVDC

Description

This demo simulates MMC-HVDC model, it has the capability to simulate in the CPU mode or in the AVM mode upon the selection of users. With the CPU mode, the detailed MMC valve will be simulated; While with the AVM mode, the averaged MMC valve will be simulated. Users can change the mode from one to another during the time of simulation. This demo is modeled using optimized RT-Lab MMC block, which can be used for half-bridge, full-bridge and clamp double MMC cells. Please also refer to the full bridge MMC STATCOM demo. The demo shows the model can simulate either off-line with much faster simulation speed comparing to other offline simulation software, or in real-time.

This demo demonstrates the MMC with HB cells, but the model can be configured to model different cell types, including half-bridge, full-bridge, clamp-double and T-type MMC cells. A half-bridge MMC (MMC-HB) cell consists of a dc capacitor, a discharge resistor, and two power electronic switches. Each switch includes an IGBT, an anti-parallel diode. The MMC block models up to maximum 50 individual MMC cells. Multiple MMC blocks can be piled up to model an MMC valve of more than 50 cells. The MMC block has following features:

The values of cell capacitance and the discharge resistance can be adjusted during simulation.
There is a dead-time between each pair of upper and lower gates.
Temporary or permanent short circuit of cell capacitor in any cells can be simulated.
There are normal mode and debugging mode. In the debugging mode, the capacitor voltages can be set to average value (to temporarily replace voltage balance control) or a fixed value.

Please refer to the help file of MMC CPU Parameter block for more information of setting relevant parameters.

The MMC subsystem is composed of MMC CPU Model Configuration block and VSC Node block, please refer to the help file for more information of setting relevant parameters. The VSC Node block is used to represent the behavior of a valve circuit based on the calculations from MMC CPU Model Configuration block. The signal interactions between the valve and the calculation block are done internally. Notices the number of VSC Node block (max 6 per converter) presented in the circuit has to match the setting in the MMC CPU Model Configuration block.

Circuit description:

The MMC HVDC is studied in a test system shown as in the two figures below.
The test system is a two-terminal MMC AC-DC-AC system linking two grids. The MMC on the each terminal has 180 cells with 30 cells per valve. The test system and MMC parameters are given in TABLE I.

Demonstration and Simulation

Various phenomena can be studied using the MMC HVDC model. In this demo model, the steady state, transients and faults can be studied. The model can be controlled and the simulation results can be monitored during simulation in the console subsystem figure.

For the control:

Pref_left	set point of the active power reference.
Qref_left	set point of the reactive power reference at Terminal 1.
Pulse_ON_left	enable or disable the PWM pulses of converter at Terminal 1.
Qref_right	set point of the reactive power reference at Terminal 2.
Pulse_ON_right	enable or disable the PWM pulses of converter at Terminal 2.
MMC para	set the MMC parameters which is explained in the previous section.
data_logging	start or stop data logging.
dcbrk	close or open the dc breaker.
ac_brk@T1	close or open the ac breaker at Terminal 1.
ac_brk@T2	close or open the ac breaker at Terminal 2.

The value of Pref_left, Qref_left and Qref_right can be adjusted between -0.3 p.u. to 0.3 p.u., by changing the values, the active and reactive power can be controlled to the desired level. Pulse_ON_left and Pulse_ON_right can be set to 1 which means the generation of the PWM pulses of converter is enable or 0 indicating the generation is disabled for the left and right MMC stations respectively.

data_logging can be set to either 1 (the data logging is enabled) or 0 (the data logging is disabled)

The status of all of the dcbrk, ac_brk@T1 and ac_brk@T2 can be set to either 1 or 0, when the breaker is set to 1, it is closed and otherwise it is opened, when it is opened, the circuit is broken from dc or ac at left or right terminal respectively.

For the monitoring:

The first scope "dc" displays respectively from the topmost to the lowermost sub-scopes:

2 signals, i.e. dc currents at positive and negative poles.
3 signals, i.e. dc voltages of positive-ground, negative-ground, and positive-negative at Terminal 1.
3 signals, i.e. dc voltages of positive-ground, negative-ground, and positive-negative at Terminal 2.

The second scope "ac side" displays following signals from the topmost to the lowermost sub-scopes respectively:

3-phase voltages at Terminal 1.
3-phase currents at Terminal 1.
3-phase active and reactive powers at Terminal 1.
3-phase voltages at Terminal 2.
3-phase currents at Terminal 2.
3-phase active and reactive powers at Terminal 2.

The scope "MMC @T1" displays following signals for Terminal 1 from the topmost to the lowermost sub-scopes respectively:

6 MMC valve voltages.
6 MMC valve currents.
6 MMC cell capacitor average voltages at each valve.
6 MMC valve voltage references from the control.

The scope "MMC @T2" displays following signals for Terminal 1 from the topmost to the lowermost sub-scopes respectively:

6 MMC valve currents.
6 MMC valve voltages.

The two displays "Vcap@T1" and "Vcap@T2", each gives 18 Vcap values. They are minimum, maximum, and average capacitor voltages of each valve (3*6) respectively.

Operating procedure:

When the system starts pre-charge, at that time all of the breakers (include dc and ac breakers) are opened, both of the pulses are off, the capacitors are pre-charged, and the dc voltage for the left terminal should be charged to around 0.6 pu.
After pre-charging of the capacitors finished, close the left terminal ac breaker, both of the pulses are off, the dc voltage for the left terminal is charged to around 0.7 pu.
Enable the pulse of the left terminal, the dc voltage for the left terminal is 1 pu.
Set the reference value of the reactive power of the left terminal, the real Q value should be the same as the reference Q value.
All the above steps are the same for the right terminal.
After finishing the above steps for both left and right terminals, close the dc breaker and see the dc voltages on both sides, set the reference value of the real power P, the real value of P should track the reference value.

Real-time Performance

The model has been run on a dual-Xeon based 3.466 GHz CPU with Red-hat operating system. The time-step is 35 µs, and 2 CPU cores have been assigned.

The model can run in 2 modes, the CPU mode and the AVM mode. The real-time simulation performance will be different with the 2 modes.

With both converters running under the CPU mode, the performance is shown as below:

With both converters running under the AVM mode, the performance is shown as below:

See Also

MMC STATCOM on CPU, MMC CPU Model Configuration block, VSC Node block

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