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MMC CPU Parameters Block
Introduction
This block sets all the relevant parameters of Modular Multilevel Converter (MMC) CPU model which can be adjusted during real-time simulation. Cell capacitance, discharge resistance, gating signals dead-time, cell capacitor mode are some parameters that can be adjusted during simulation. In addition, users can switch between two valve modeling modes: 1) detailed MMC valve mode, and 2) valve equivalent with average value model (AVM). In detailed MMC valve mode, the detailed switching phenomenon and individual cell voltages are modeled, whereas in AVM the submodules capacitors are replaced with a valve equivalent capacitor which can further improve computation efficiency.
Mask and Parameters
Common
Name | Description | Unit | Variable = {Possible Values} | |
---|---|---|---|---|
Select model type | This option is selected for the model operating in different modes:
| {0, 1} | ||
Cell capacitor [Farads] | Capacitance of each cell capacitor in Farad | Farad | >0 | |
Discharge Resistance of cell capacitor [ohms] | Discharging resistance in ohms | Ohm | >0 | |
Vcap mode | This option is selected for different operation modes of the capacitors:
| {0,1,2,3} | ||
Vcap fix value (SI) | The fixed value set when Vcap is in mode 3, i.e., Vcap set to a fixed value. | Volt | >=0 | |
Enable pulse | Enables the gating signals. | |||
G5 ON (check)/OFF (unchecked) | For all clamp double submodules, enables gating signal of S5 switch, i.e., G5 |
CPU
Name | Description | Unit | Variable = {Possible Values} | |
---|---|---|---|---|
SM type | Specify the submodule (SM) or cell type of the converter
| |||
number of SM (nb must match parameter set in SM block) | Specify the total number of SMs per valve (for Clamp Double SM, the number of SM should be equal to the number of capacitor) | maximum value is 50 | ||
VBC mode | Voltage Balance Control (VBC) mode: mode 1: only switch 1 SM with maximum or minimum capacitor voltage at each step if the reference number of ON SM is different than the actual value. mode 2: SMs are ON or OFF according to sorting results of SM capacitor voltages. | |||
VBC error (only for mode 1) | In mode 1, if the reference number of ON SM is same as the actual value and the SM with maximum or minimum capacitor voltage has its voltage difference from the nominal voltage more than the VBC error, the SM is switched. | pu | [0,1) | |
PWM (unchecked) or NLC (checked) | If unchecked, gating signals are generated by pulse width modulation (PWM) method; and if checked, gating signals are generated by nearest level control (NLC) method. | |||
Keep cell short-circuit upon error | If checked, if a short circuit happens to an SM its capacitor is considered to be damaged and its voltage id kept at 0. | |||
IGBT deadtime (pu of Ts, [0,1)) | Deadtime of IGBT pairs. For example, for 25 μs simulation time-step and 5 μs deadtime, the value will be 5/25 =0.2. | pu | [0,1) |
AVM
Name | Description | Unit | Variable = {Possible Values} | |
---|---|---|---|---|
Number of HBSM | Number of half-bridge SM (cell) | |||
Number of FBSM | Number of full-bridge SM (cell) | |||
Number of CDSM | Number of Clamp double SM (cell) |
Inputs, Outputs and Signals Available for Monitoring
Inputs
There is no input for this block.
Outputs
Name | Description |
---|---|
MMCPara | Configuration signals sent to MMC CPU block and VBC subsystem. |
Description
Limitations
For this block, the maximum number of submodules that can be set for each valve is 50.
See Also
OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
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