Test Design for Full Bridge Topology

• Full-Bridge Topology Maximum Cell Number Test
• Full-Bridge Topology Vcap Display and MMC PULSE Block Test
• Full-Bridge Topology Vcap Mode Test
• Full-Bridge Topology Fault Signals Test
• Full-Bridge Topology Cell Capacitance Verification
• Full-Bridge Topology Cell Shunt Resistor Verification
• Full-Bridge Topology Switch Ron Verification

In this version of MMC models, we are able to simulate both of the half-bridge sub-modules and the full-bridge sub-modules.

This test is designed to ensure the two modes of sub-modules can work properly. 

The full-bridge sub-module (FBSM) topology is shown in the figure: it can be shown that in full-bridge sub-module, there are 4 gates, signals of G1 and G2 are complementary and signals of G3 and G4 are complementary, thus in the pulse control of the model, we only control G1 and G3.

For thorough, reliable tests, seven kinds of tests are designed, and outlined below:

1. Maximum cell number test; Vcap observation and Gate Signals block test; 
2. Vcaps mode test;
3. Pulse source test;
4. Fault mode test;
5. Cell capacitance test;
6. Resistance in shunt with the cell capacitor test;
7. Switch Ron test;

At the beginning of each designed test, the system should be initialized. 

Initialize the Parameters of MMC Parameter Block

MMC parameter block initialization setup

Then...:

• Initialize the parameters of Arm Current Generation block as in the table.
• Keep all signals off both in Gate Signals block and MMC Fault block.