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Test Design for Full Bridge Topology

In this version of MMC models, we are able to simulate both of the half-bridge sub-modules and the full-bridge sub-modules.

This test is designed to ensure the two modes of sub-modules can work properly. 

The full-bridge sub-module (FBSM) topology is shown in the figure: it can be shown that in full-bridge sub-module, there are 4 gates, signals of G1 and G2 are complementary and signals of G3 and G4 are complementary, thus in the pulse control of the model, we only control G1 and G3.

Full-bridge topology of the sub-module

For thorough, reliable tests, seven kinds of tests are designed, and outlined below:

  1. Maximum cell number test; Vcap observation and Gate Signals block test; 
  2. Vcaps mode test;
  3. Pulse source test;
  4. Fault mode test;
  5. Cell capacitance test;
  6. Resistance in shunt with the cell capacitor test;
  7. Switch Ron test;

At the beginning of each designed test, the system should be initialized. 

Initialize the Parameters of MMC Parameter Block

MMC parameter block initialization setup


Set value


SM type

1: Full-bridge

Tests for full-bridge topology sub-modules

cell capacitance (farads)


A test value, may vary

switch Ron (ohms)


Remove voltage drop on Ron

capacitor shunt resistance (ohms)


Disable discharge by Rshunt

Number of cell per arm


Total number need to be tested

Capacitor voltage base


Set capacitor voltage base to 1

Vcap mode

Set to fixed value

To initialize and fix the Vcap=Vcap value

Vcap fix value (pu)


To initialize and fix the Vcap=0

Pulse source

Direct gate signal from CPU

Control cells using Gate Signals block


  • Initialize the parameters of Arm Current Generation block as in the table.
  • Keep all signals off both in Gate Signals block and MMC Fault block.

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