In this version of MMC models, we are able to simulate both of the half-bridge sub-modules and the full-bridge sub-modules.

This test is designed to ensure the two modes of sub-modules can work properly.

The full-bridge sub-module (FBSM) topology is shown in the figure: it can be shown that in full-bridge sub-module, there are 4 gates, signals of G1 and G2 are complementary and signals of G3 and G4 are complementary, thus in the pulse control of the model, we only control G1 and G3.

For thorough, reliable tests, seven kinds of tests are designed, and outlined below:

Maximum cell number test; Vcap observation and Gate Signals block test;
Vcaps mode test;
Pulse source test;
Fault mode test;
Cell capacitance test;
Resistance in shunt with the cell capacitor test;
Switch Ron test;

At the beginning of each designed test, the system should be initialized.

Initialize the Parameters of MMC Parameter Block

MMC parameter block initialization setup

variables	Set value	Reason
SM type	1: Full-bridge	Tests for full-bridge topology sub-modules
cell capacitance (farads)	0.01	A test value, may vary
switch Ron (ohms)	0	Remove voltage drop on Ron
capacitor shunt resistance (ohms)	1e12	Disable discharge by Rshunt
Number of cell per arm	10	Total number need to be tested
Capacitor voltage base	1	Set capacitor voltage base to 1
Vcap mode	Set to fixed value	To initialize and fix the Vcap=Vcap value
Vcap fix value (pu)	0	To initialize and fix the Vcap=0
Pulse source	Direct gate signal from CPU	Control cells using Gate Signals block

Then...:

Initialize the parameters of Arm Current Generation block as in the table.
Keep all signals off both in Gate Signals block and MMC Fault block.

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