This test is designed to determine whether the V_cap display and the assignments of Gate signals can work correctly.

To achieve the test purpose, we can observe the variation of the value of V_cap in the V_cap Display block after fixing the V_cap to a value (for example 1 p.u.), and at the same time, pay attention to the variation of the value of Total V_cap.

System initialization.
To test the 1^st group of cells per arm, just change the number of per arm to 16, as shown in Figure 33.
Check Vcap display block as shown in Figure 16.
In MMC Parameter block, change V_cap fix value to 1pu. And for MMC full-bridge topology sub-module, the gate signals are for G1 and G3 respectively as shown in Figure 34. The table shows the output voltage when with different input gate signals:

FBSM gate signal for output voltage

G1	G3	Output Voltage
0	0	0
0	1	-Uc
1	0	Uc
1	1	0

In the first test, keep the G3 of the 16 cells zero and enable G1 them one by one, if the output voltage increases by one each time, it shows the MMC pulse block works correctly:

In the second test, keep the G1 of the 16 cells 0 and enable G3 of them one by one, if the output voltage is negative and the absolute value increases by one each time, it shows the MMC pulse block works correctly:

In this test, we enable or disable all the pulse signals for G1 and G3 of the 16 cells, if the results are zero, it shows the pulse block works correctly:

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