Software and Versions

• To open, edit and execute the MMC FPGA model, the following software has to be installed
  
  • Matlab /Simulink Matlab 2011b
  • Xilinx System Generator Version 14.7 recommended
  • RT XSG Version v2.2.6.61 4 (R2007b R2011b (for OP4510, Version v2.3.0 and above)
  • eFPGAsim Version v1.4.3 ( R2011b
• To generate the bitstream, the following software has to be installed with a license
  
  • Xilinx ISE Design suite: System Edition (v14.7 recommended) http://www.xilinx.com/products/design tools/ise design suite.html ) or any edition with System Generator for DSP included.
  • Matlab /Simulink Matlab 2011b 64 bit recommended (for generating bitstream only)

Prerequisite and Goal

• Prerequisite
• OP102 RT XSG
• Goal of this training
  
  • to help user understand the differences between modelling in Simulink and XSG environments and master the concepts, principle, and basic function blocks used in MMC FPGA model.
• Expectation of this training
  
  • Through demos and hand on exercises, the user should be able to understand the provided MMC FPGA model, to modify the model, and to add new function blocks and subsystems in the model.

RT-XSG Review

• Signal data type
  
  • Possible type: fixed point or float point (note double type in Simulink)
  • Fixed point used in MMC model
  • Precision: each signal is defined accordingly if it is signed or unsigned, number of bits, and binary point.
• Pipeline dataflow in FPGA
  
  • Each XSG block could have a latency of zero or a few FPGA clocks
  • Delay (latency) is mandatory after series connection of a few XSG blocks, or timing error at bitstream generation
  • 1 model time step != 1 FPGA clock
  • Synchronizing between paths of different latency
• Calculation in parallel and series
  
  • Multiple functions for parallel calculation, more FPGA resources
  • Calculating in series by time multiplexing (muxing)

Example 1: Signal Data Type

• Open and run hand on example 1
• Understand
  
  • What does this function do?
  • Which part is for RTXSG model? Which is for Simulink model?
  • Why the results are different? How to correct it?
  • The function of blocks of “Gateway in”, “gateway out”, and “system generator”.

• What does this function do? <a*b+c>
• Which part is for RTXSG model? <A> Which is for Simulink model? model?<B>
• Why the results are different? <signal A data type precision is not enough> How to correct it? <redefine the data type as in the
• The function of blocks of “Gateway in”, “gateway out”, and “system generator”. <refer to RT XSG training>

Example 2: Signal Delay and Synchronizing

• Open and run hand on example 2
• Understand
  
  • What does this function do?
  • Why the results are different? How to correct it?

• Problem?
• Pipeline in FPGA
• What is pipeline?
  Baidu:
  https zhidao.baidu.com/question/252324226.html
  In hardware the function of pipeline is implemented by inserting registers in the combinational logic. Long combinational path tends to cause low maximum frequency. If there is critical path in your design, you can use the pipeline to insert registers in the long combinational path to shorten it. Then the timing performance will be improved.
  翻译一下，大概意思就是：流水线就是在延时较长的组合逻辑（一般是
  多级组合逻辑）中插入寄存器，将较长的组合逻辑拆分为多个较短的组
  合逻辑，以提高设计的最大时钟速率。流水线的缺点是会在设计中引入
  流水线延时，插入一级寄存器带来的流水线延时是一个 时钟周期
• Problem? Pipeline

• solution

• What does this function do? < a*b+c>
• Why the results are different? <different signal delay at different path> How to correct it? <synchronizing by adding delay at different path>
• Note Latency between input and output is 4 FPGA clocks

Example 3: Triangle Carrier Signal

• How to generate a triangle carrier signal using XSG library blocks?
  
  • Start with hand on example 3. You can use any blocks in XSG library for your own design.

• Triangle carrier signal generation: example 3.1.
• Check the signal type of block output signals;
• Predict the waveforms in signals A, B, and C;
• Simulate the model and verify the waveforms in A, B, and C;
• Compare this example with your design;
• Can this addsub2 block be replaced by a simpler operation?
• How to change carrier frequency?

• Triangle carrier signal generation:.
• Can this adder/subtracter block can be replaced by a simpler operation?
  Example 3.2: Replacing with a inverter block.

• How to change carrier frequency? By changing the incremental value of the adder (input b)
• To set the carrier frequency to be 3000 Hz, what is the input? (FPGA clock is 5 ns)
• What is the resolution of the tunable frequency?
• Triangle carrier signal generation:.
• To set the carrier frequency to be 3000 Hz, what is the input? (FPGA clock is 5 ns 2/x=(1/ frq)/ Tclock x=2* Tclock frq =2*5e 9*3e3=3e 005
• What is the lowest carrier frequency?
  Frq_min
  x_min /( Tclock
  For UFix32_31,
  x_min =2 31, (note the precision depends on the input block
  and the adder block.)
  Thus,
  Frq_min = 31/(2*5e 9) = 0.0466 Hz
• What is the resolution of the tunable frequency?
  Frq
  = ( x_min 2* Tclock
  For UFix32_31,
  x_min = 31, => Frq = N*2 31/(2*5e 9) = N*0.0466 Hz
  Thus resolution is
  0.0466 Hz.
• How to have multiple interleaved carriers?
• Multiple interleaved carrier signal generation:.
• Delay
  More resources
  Variable delay number at different carrier frequency
• Offset
  Less resources
  Tunable phase shift by changing the offset value

Example 4: Time Muxing and Demuxing

• Open and run hand on example 4
• Understand
• What does this model do
• There are 4 instances of same function: parallel computation
• The “Multiplier” block takes FPGA resources. how to save them?

• What does this model do? < pulse generation, the signal multiplied by 0.9 and compared to the carrier>
• how to save FPGA resources? < using time muxing and demuxing>

• Open example 4 1. Understand the model: one instance of function works for 4 signals
• How signals are time muxed and demuxed
• Observe the signals. Why pulse 1 doesn’t match the original? How to correct?

• Why pulse 1 doesn’t match the original? signals are not sync >How to correct? < sync by delay>
• Now, is there any difference between the time muxed and demuxed pulse 1 and the original pulse? If yes, what is the difference?

• What is the difference between the time muxed and demuxed pulse 1 and the original pulse?
  Signal resolution: 1 FPGA clock for original pulses; 4 FPGA clock for time muxed and demuxed pulses
• To implement N times of identical calculation:

• More often, a mixed implementation will be chosen to compromise between FPGA resources and calculation time step. N=P*Q calculation is implemented by P function instances in parallel, each handles Q in series.

Example 5: Pulse Dead Time

• Thinking in Simulink
• Example: without dead time g2= NOT(g1)

• How to implement dead time?
• Simulink e xample: dead time
  g1_dt= AND(g1,delay(g1,deadtime));
  g2_dt= NOR(g1,delay(g1,deadtime));
  The delay is the dead time interval

Practice:

• Implement the same logic in FPGA model.
• Generate dead time for 4 inputs by using time muxing and demuxing technique.

• Deadtime in FPGA model

• Deadtime with time muxing and demuxing

• How to change deadtime interval, e.g. 9 FPGA clocks?
• How to change deadtime interval, e.g. 9 FPGA clocks?
  Change # of delay corresponding to the dead time interval.

•

• Why does it work for single function, not for time muxed function?
• How to change dead time interval during simulation? (variable dead time interval without recompilation of bitstream.)
• What is # of delay if dead time is 5 us? ( Tfpga = 5ns)

Solution:

• How to change dead time interval
• What is the maximum DT interval
• If 50 signals are time muxed , what modification need to be done?

• How to change dead time interval?
  dead time interval = # of delay * 4 * Tclock
  Validate in the model
• What is the maximum DT interval?
  dead time interval_max= (# of delay )_max* 4 * Tclock 2^16*4*5e 9=1.3 ms
  UFix16_0 is enough for the adder
• If 50 signals are time muxed , what modification need to be done?
  The delay number has to be changed to 49.

Mcode Block

• In the Xilinx Blockset Control Logic, Math, and Index library
• The Xilinx MCode block is a container for executing a user supplied MATLAB function within Simulink
• More on help
• Example: C: Xilinx 14.3 ISE_DS ISE sysgen bin xlmax.m
  function z = xlmax (x,y)
  if x > y
  z = x;
  else
  z = y;
  end
• Exercise: using other basic Xilinx blocks to make the same max function logic

• some Mcode used in MMC models
  
  • efsMultiSliceBlock.m
  • efsBitReorderBlock.m
• efsMultiSliceBlock.m
• To slice off multiple equal bit outputs from input
  Sin: input signal
  startwithLSB : =1,start with LSB; =0, start with
  MSB, to be implemented in future release :
  nbofOutput: number of outputs,
  bitperOutput: number of bit in each output
  for example, Sin=110011001100,startwithLSB
  =1, nbofOutput =4, bitperOutput =3
  output: z0=100;z1=001;z2=011,z3=110;

• efsBitReorderBlock.m
  To reorder the sequence of the input signal Sin.
  the dimension of Sin>= K*M*N , only (K*M*N) LSB is used, the bits more than
  K*M*N are not used. the dimension of the output signal Sout is exactly K*M*N.
  normally the M*N number of K bit elements as below

Sin is [extra bits not used , S M*N , S M*N 1 ... , S N+1 S N , ... , S 2 , S 1
Sout is S M*N , S (M 1)*N ... , S 2 S (M 1 N+1 , ... , S N+1 , S 1
for example, Sin =[ hex , each digital is represented by 4 bits, total 24 bit,if K=4,M=3,N=2; output: Sout 642531] hex if K=4,M=2,N=3; output: Sout =[635241] hex;

Example 6: Mcode

• Understand the model
• Predict the signal
• Simulate the observe the waveforms

• waveforms