RT-LAB 2024.4.0

Software Toolboxes Installed with

Added

• Added the detection of running simulations launched by a different user on a target.

• Added a new EXata example model.

Improved

• Added the ability to retry when the installation of MinGW fails.

• When using a OpWriteFile add a warning if the generated .mat file exceed the limit of 100 millions elements to avoid file corruption.

• Kept the MATLAB window messages and warnings when opening it from RT-LAB.

• Improved performance of Api call:

  • GetConnectionsPointsForIO

  • LoadParameter

  • LoadSignal

  • FindParameter

  • FindSignal

  • FindBlock

• Improved the progress information displayed during RT-LAB installing on a target.

• Improved the recovery after an abrupt closing of RT-LAB UI when restarting it.

• Improved the displayed error message where the console is opened when building a model.

• Improved internal handling of files generated when compiling models.

Fixed

• Fixed the Discover targets feature not allowing to add multiple targets sharing a same default host name.

• Fixed the installer partially installing the product in case of an internal failure.

• Added missing Api functions to the documentation.

• Fixed issue related to LabVIEW Panels connections disappearing after second model reload after a reset without closing the panels.

• Fixed the Help center page formatting and missing RT-LAB logo.

• Fixed issue preventing the use of signal monitoring tools (ScopeView, Dataviewer) when RT-LAB GUI is open.

• Fixed an issue where the recorder is not usable after renaming the model.

• Fixed Orchestra C_code example model execution on target.

• Fixed an issue with the opening of Simulink console when a model was in mdl format and used with Matlab 2022a and following.

• Fixed an issue in the ProbeControl that could result in incorrect signal selection when the model is recompiled.

• Fixed an issue where RT-LAB freezes at the end of compilation step after an update of the eHS block.

• When assigning different targets for different subsystems in Assignments tab of the model, the subsystem list in Project Explorer view does not update until the project is manually refreshed.

• Fixed issue where the Model can be started from Dashboards whereas not yet compiled from the right platform.

Dashboards - Signal Visualization and Processing

I/O Interfaces

• Improved stability by ensuring that asynchronous computation components of I/O interfaces run either on core 0 or on a dedicated core, but not on the core of the simulation itself

CAN

• Fixed regression found with message multiplexing

• Fixed value provided in the ‘No message’ connectable

FPGA drivers (common changes to OPAL-RT Board and OpCtrl S-Functions)

• Added the display of extra information such as the IP and MAC addresses to the detection of OP4810-IO/OP4815-IO platforms.

• Improved workflow by skipping bitstream programming if OP4810-IO/OP4815-IO platforms are configured with an empty chassis name and/or an empty IP address.

• Fixed wrongly found hardware mismatch for extra slot of OP4810-IO/OP4815-IO platforms.

FPGAScope

• Fixed capability to differentiate boards of the same family type.

• Fixed crash of simulation when using an RT core.

GT200

• Added support for the SCRAMNet GT200 shared memory card.

IEC 60870-5-104 Slave

• Added support for timestamped commands for normalized, scaled and floating points.

MODBUS Slave

• Added support for TCP slave IDs up to 255.

OPAL-RT Board

• Added capability to program multiple OP4810-IO/OP4815-IO platforms in parallel during the load of a model.
  Note: This feature is only supported with one Simulink subsystem on one target.

• Improved workflow by keeping connections even if a raw data point's name changes.

• Fixed overruns appearing when splitting MuSE connections on multiple subsystems.

• Fixed bitstream configuration update mechanism to:

  • keep the name of raw data signals;

  • keep the byte and bit offsets of raw data signals;

  • keep the state of the ‘Enable FPGA scope’ check-box;

  • support merging configurations for OP48H20 cards.

• Fixed filter for bitstream file browser.

• Fixed wrongly displayed message about firmware mismatch.

• Fixed validation of threshold limits for digital channels.

PICKERING

• Added support for the 40-297A-040 and 40-262-002 programmable resistor cards.

S-Function IOs

• Improved usability by validating that the IO functionality blocks are using the correct data ports.

• Improved usability of OpCtrl and OpLnk blocks by increasing the timeout needed by their initialization sequences.

• Fixed configuration of analog out multi-range for slot 1B of TE0741 type boards.

• Fixed PWM inputs when mapped on the first data port.

Synchronization

• Fixed logs that were referencing the wrong network interface used by the Oregano card

ARTEMiS - CPU-Based Electrical Toolbox

• Improved the example model SSN_NewEngland39busRT to support online simulation.

• Corrected the online behaviour of TSB-RD 2-Level block.

• Fixed the example model of Artemis Banshee.

• Fixed the example model ssn_TrainTractionDrive_AE for online use.

• Fixed the example model SSN_4Terminal_MMC_DCgrid.

ePHASORSIM - CPU-Based Phasor-Domain Toolbox

• Migrated Excel templates in examples to template version 2.0 - OUDS-2774: Support excel v2.0 - without FMU (ePH)Closed.

FPGA-Based Power Electronics Toolbox

eHS Blockset

Added

• Added support of de-coupling capability of large circuits for eHS Gen5 High Performance (more details).

• Added support of machine resolver double excitation for PMSM and BLDC machine models.

• Added the number of States used by the circuit in the Build report.

• Added support for multiple AIR blocks in firmware.

• Power System - FD Line Bitstream for OP4815 platform.

Fixed

• Added back the ‘Open Log’ button in the MATLAB error window.

• Fixed Dual Active Bridge example model giving now correct results.

Deprecated

RT-XSG Blockset

Added

• Added support for Vivado 2024.1.

• Added support for Matlab 2022b and 2023a.

Fixed

• Improvement of the integration of OP5369 DIO boards in RT-XSG.

• Performance optimization of the bitstream generation process.

• Improvement of the integration of the “Selectable Digital“ application blocks in RT-XSG.

• Improvement of the automated generation of configuration files for eHs.

• Improvement of the MuSE performances for the 7Series based platforms.

• Improvement of the SFP communication for the OP4810/OP4815 simulators.

MMC Blockset

Added

• Added bitstream of Versal FPGA VM1402 and updated bitstreams including new features, e.g. SM dc current injection, individual control of fast discharge of SM in FPGA.

• Added a unitary CPU MMC test model and updated document for FPGA MMC unitary test procedure. 

Improved

• Improved MTDC MMC demo, i.e. changing the slack bus from dc bus 2 to bus 1 for better system performance in some operating scenarios.