RT-XSG 3.x Evolution

• OP5#07 v.3. prototype
• HCIG v1

• OP5#07 v.3.
• BiSS-C (BETA)
• SSI (BETA)

• MuSE BETA
• OP5143 BETA

• MuSE (functionality): OP5600/OP5143, OP5650
• Multi-voltage ranges analog output bug fix
• Polymorphism enable support

• Mezzanine list - "empty" on top
• Multi-rate support correction
• HCIG support of Goto/From and bus selector blocks
• MuSE
• larger DMA transfer size
• enumeration improvement
• Addition of model examples (OP5650)

• Communication through DataIN/DataOUT blocks with 64 ports support (except for OP4200)
• OP7000v2 BETA support (Primary FPGA board)
• OP5367 (LoadIn) 16 x DIN with programmable threshold and 16 x DOUT mezzanine for OP4510 only (BETA)
• Endianness options addition for Generic Aurora communication
• OP5332 with 200 MHz bug fix for loading EEPROM gain and offset values
• OP5650 - Fixed synchronization pulse (Artix-7)

• Default Output Values (DOV) support
• OP7000 V2 Primary FPGA board support (Kintex-7 XC7K410T-2FFG900)
• New Architecture "No MuSE" for OP4510/325T,410T and OP5#07
• HCIG update with Resolver support

• Improvement by providing designer help by warning the DataIN/OUT blocks configurations without FIFO use (FPGA-345)
• Added protection in user interface of DataIn/DataOut blocks to warn the user to use FIFO mode when the blocks are connected to analog I/O blocks (FPGA-345, 346)

Vivado 2019.2

Matlab 2019b

• SPI block support
• OP5367(LoadIN), 16 Digital IN with programmable threshold and 16 digital OUT support for OP4510 only
• OP5334, 16 analog OUT 2 MSPS non-isolated beta support for OP5650, OP5707, OP4510 and OP4200
• HCIG update with Time Stamp Bridge (TSB) support
• Vivado 2019.2 with MathWorks Matlab 2019a and 2019b BETA support
• Obsolescence warning on Vivado 2015.3 and 2015.4 with Matlab 2014b, 2015a and 2015b next RT-XSG revision

• HCIG: IEC60044-8 support.
• Bitstream's generation: constraints application fix (FPGATT-595) and error reporting (FPGATT-592).
• OP5342 at 2.000 MSPS in OP4200 with CPU at 1 GHz and FPGA at 200 MHz (FPGA-427). It was 1.98 MSPS.
• DOV: Enabled the resize of the configuration window (FPGATT-369).

• Aurora block had a wrong parameter's value.
• OP5342 timing for all FPGAs.
• Compatibility with R2016b.

• Added new FPGA Acquisition module during bitstream generation, enabling acquisition of signals internal to the RT-XSG model at an acquisition rate higher than the CPU-based simulation rate.
• OP8110 (ZX5_AMPLI_4Q) beta support.
• OP5369 beta support.
• Fixed regional time settings error by specifying the "datestr" function to use the 'local' system's parameters (FPGATT-638).
• Fixed on reporting error leading to a status=11 on compiling DOV source (FPGATT-638).
• Fixed 2019b support by not using the same name (FileReader) as a class name and a variable name (FPGATT-624).

Features

• OP5369 Digital configurable direction and threshold - 32 channels, for OP4510, OP5707 and OP5650.
• Aurora CRC error injection option.
• XilinxVivado 2020.1 BETA support.
• MathWorks Matlab 2020a BETA support.

Bug fixes

• Known limitation on the OP5369 threshold values programming, on Load state, the values can be not programmed, there are Python scripts that are available for fixing values with OPAL-RT Support assistance (FPGATT-858).
• OP5650 - Artix-7 New Gray Zone lightened for having more FPGA resources (without MuSE neither Aurora) (FPGATT-848).
• Remove Vivado "Advanced sub-tool" options, available for advanced users, options managed by an environment variable (FPGATT-847).
• Copy of an IO Block configuration loss correction (FPGATT-833).
• MuSE Robustness on SFP cable disconnection and unlock faulty Remote programming (instead of a Central).

Vivado 2020.1, 2020.2

Matlab 2020a, 2020b

Features

• Xilinx Vivado 2020.1 and 2020.2 support
• MathWorks MATLAB R2020a and R2020b support
• OP5330 configurable rate (not only determined by the bitstream anymore)
• OP5033XG / Industrial PC without IOs support - OP5143 FPGA Board with Artix-7
• Limiting search of DCP-files to RT-XSG model folder (no more sub-folders)
• Improved time of Simulink and Vivado regarding SDI and SDO logic
• HCIG: Resolver feature when automatically generating .opal file
• Retro-compatibility and usage of I/O Blocks

Vivado 2021.1, 2021.2

Matlab 2021a

AMD-Xilinx Vivado Model Composer 2022.1

MathWorks Matlab 2021b

Bug fixes

• Increase a configuration watchdog timer for accommodating a big uncertainty on the Xilinx internal oscillator for Kintex-7 410T (FPGATT-1170).
• Clock domain formalization for covering sporadic issues on analog board's EEPROM content loading for Artix-7 (OP5143) FPGA-based simulators  (FPGATT-1210).

Features

• Added IOCONF file auto generation with the basic blocks for custom application in RT-XSG design (FPGA-473)
• New SPI slave block allowing different sizes of MISO and MOSI. New design also allows to receive and send messages at different times (FPGATT-1236)
• New I2C Master and Slave blocks (FPGATT-1240)
• Added Digital Input card OP5367-6, which is a variation of the OP5367-5 with 10x its impedance, and a different board Id (0xE6) (FPGATT-1326)

Bug fixes

• Fixed unresolved links in OP5367 IO Block library (FPGATT-1205)
• Fixed the bitbasher on the 2nd channel for Sine_in in the Resolver Input Subsection block (FPGATT-1179)
• Clock domain formalization for covering sporadic issues on analog board's EEPROM content loading for all FPGA-based simulators (FPGATT-1318)

Removal

• Removed support for Vivado 2017.x and MATLAB R2016b and R2017a. New minimal supported versions are therefore Vivado 2018.1 and MATLAB R2017b (FPGA-1368)
• Removed support for OP4200 (FPGA-1366)

Features

• Added Digital Input oversampling clock (FPGATT-1291)
• Added new and improved Resolver In block (FPGA-1343)
• OP5369 -> OP5351 Asymetric Polymorphism (FPGATT-1387)

Bug fixes

• Changed EEPROM I2C frequency to 100 KHz in order to avoid its corruption (FPGATT-1335)

AMD-Xilinx Vivado Model Composer 2023.1

MathWorks Matlab 2022a

Features

• Support for AMD Versal Prime series VM1302 and VM1402
• Added support for unmuxed format for AIn Packing and AOut Packing blocks
• Modified Resolver Subsystem In and Out blocks with new interface to be compatible with different I/O formats

Bug fixes

•  Fixed the FPGA Scope crash when we kill and restart FPGAScopeTool manually, or when we reset and load the simulation

Features

• Added support of the IO card OP48H20 "standard" (AIO/DIO/HCIG-OPALBOARD)

Bug fixes

•  Synchronization pulse reinforced for avoiding signal width reduction through several daisy chained simulators ("7-series", except for Artix-7, Versal)

ARM core configuration

• Versions
  
  • Targeted to the Cortex R5 processor with the AMD Vitis IDE version v2023.1.0
  • The Real-Time OS freertos10_xilinx version 1.13, based on the FreeRTOS kernel version 10.5.1
• Supported features
  • The phy_link_speed configuration is 1000 Mbps
  • Boot mode: QPSI (default), JTAG, SD CARD
  • LCD display:
    • ID, IP, Subnet, .elf version number
    • Project Name & Simulation status
  • The flash bitstream update: update bitstream in QSPI and soft reboot
  • Access to Gray zone registers: limited, only access to Chassis ID and simulator status
• Bug fixes
  • Resolved freeze issue that could occur during the reset operation
  • Resolved memory allocation
• Known limitations

  • Control over the User-Zone design is not supported

  • Stand alone application is not supported

AMD-Xilinx Vivado Model Composer 2024.1

MathWorks Matlab 2022b, 2023a

Features

• Access to Grayzone Registers form ARM core user application for both read and write
  (FPGA-1468) 
• AMD-Xilinx Vivado, ModelComposer, 2024.1 (FPGA-1470)
• MathWorks MATLAB R2022B, R2023A (FPGA-1470)
• Added 64 ports mode polymorpism for OP5369 (FPGATT-1439)
• RT-XSG Module Port blocks can now pass over Xilinx Delay blocks during connection
  creation for ioconf generation

Bug fixes

• - RT-XSG Simulink model optimizations (FPGA-1431)
• Fixed support of multiple bus selectors on same depth or AppConfigRegister (FPGATT-
  1569)
•  Fixed missing Simulator file on OP481x platform (Versal) ioconf generation
•  Fixed AO, AI and DI generation on OP481x platorm (Versal) ioconf generation
• Fixed generated binary file extension (.pdi instead of .bin) on OP481x platorm (Versal)
  ioconf generation
• Fixed overruns when using MuSE with more than 45 dwords transerred per port with
  32 or more ports (FPGATT-1136)
• Fixed time-out when loading model using OP4610 in MuSE remote (FPGATT-1555)
• Fixed abnormal values during SFP communication between OP4810/15 and OP5700
  (FPGA-1479)
• Removed SFP ports from OP48H10 example model to keep some place for MuSE
  (FPGATT-1556)

ARM core configuration

• Versions
  
  • Targeted to the Cortex R5 processor with the AMD Vitis IDE version v2023.1.0
  • The Real-Time OS freertos10_xilinx version 1.13, based on the FreeRTOS kernel version 10.5.1
• Supported features
  • The phy_link_speed configuration is 1000 Mbps
  • Boot mode: QPSI (default), JTAG, SD CARD
  • LCD display:
    • ID, IP, Subnet, .elf version number
    • Project Name & Simulation status
  • The flash bitstream update: update bitstream in QSPI and soft reboot
  • Access to Gray zone registers: limited, only access to Chassis ID and simulator status
  • Full access to Gray zone registers
• Bug fixes
  • Resolved freeze issue that could occur during the reset operation
  • Resolved memory allocation
• Known limitations

  • Control over the User-Zone design is not supported

  • Stand alone application is not supported

Bug fixes

• Fixed overruns when using more than one remote with one central (FPGATT-1632)
• Fixed an error in .opal when having only one OP48H10 card in hardware manager (FPGATT-1629)
• Fixed DOV error for OP48H10 analog out (FPGATT-1621)
• Fixed timestep error for OP481X platforms (FPGATT-1614)

Features

• Added support for new OP4300-2 simulator (PJ000379-207)
• Added support for OP4810 and OP4815 MuSE remote architecture (PJ000324-910)
• Added description of the hardware used in the bitstream inside the ioconf file (EFS-8179)
• Generate the correct uuid for the ioconf file automatically (EFS-8061)

Bug fixes

• Replaced deprecated command for implementation strategies for Vivado 2024.1 (FPGATT-1665)
• Fixed scaling issue in DOV display when zoom is not 100% mode (FPGATT-1652)
• Fixed DOV bug for OP48H10 Analog Out where "Keep Value Unchanged" mode behaved like "Assigned Value" mode instead(FPGATT-1650)
• Fixed inconsistencies in DOV menu warnings when stepping out of permitted range for "Assigned Value" mode (FPGATT-1647)
• Added warning when choosing MuSE Central for OP4810 and OP4815 since the functionality is not yet available (FPGATT-1646)
• Fixed timing issues caused by mismatch in clock domains when using oversampling (FPGATT-1623)
• Fixed rate transition block behavior when sending only one data (FPGATT-1605)
• Fixed issue where RT-XSG would change the Matlab current directory even when setup_rtxsg script failed (FPGATT-783)
• Changed the order of RT-XSG Module out signals by pin number instead of name (EFS-8228)

Features

• Added support for OP4810/OP4815 as MuSE Central and Remote. Note that OP481x cannot be used as MuSE Central with 7-Series Remote
• Added support for new product OP4300-IO product

Bug fixes

• Fixed erroneous mapping of FPGAScope probes onto OP48H10, OP48H20, OP4300 ADCs (FPGATT-1665)
• Application Config Register fix for SDI when signal is being packed in a bus creator but not named at the same level (FPGATT-1674)
• Fix for Generic Aurora Block not making clocks available in GUI when not supported by chosen simulator (FPGATT-1668)
• Fix for Generic Aurora Block not making Line Rates available in GUI when not supported by chosen simulator (FPGATT-1680)
• Library standardisation of RT-XSG library hierarchy in library browser (FPGATT-1648)
• Added missing User LED lib for OP48XX in the library browser (FPGATT-1612)
• Fixed issue where display of LCD of OP481X dissapears when Ethernet cable is unplugged (FPGATT-1607)
• Fixed issue where RT-XSG wasn't getting set up in Matlab environment when Matlab or RT-XSG is first installed on PC (FPGATT-1714)
• Fix for access to shared registers from ARM cores in OP481X Remote (FPGA-1653)