Block

Mask

Mask

Description

This block implements a 3-phase inverter model on the RT-XSG-compatible card. The inverter has a high-impedance mode to simulate the rectifying mode of this type of converter when all IGBT pulse are OFF.

The model has a minimum latency of 8 FPGA clock cycles (18 cycles if Ron > 0 and Vf > 0).

Parameters

Inverter base voltage (in V) and base current (in A)	Rated voltage (in volts) and current (in amperes) of the devices.
Voltage offset (V)	Voltage offset of the IGBT or diodes when in conduction (in volts). A null offset voltage minimizes FPGA resource usage as well as latency.
Switches ON Resistance (Ohms)	Conduction resistance (in Ohms), equal to the conduction resistance in Ohms divided by the impedance base. A null ON Resistance minimizes FPGA resource usage as well as latency.
Implement DC link current module	When positive, implements the DC-link current calculation module. Set to ‘no’ if working with a fixed voltage DC-link and/or if DC-link current is not used to optimize FPGA resource usage.

Inputs

Vdc	DC link voltage in pu and in Fix18_15 format.
Ia	Machine current for phase A in Fix18_15 format.
Ib	Machine current for phase B in Fix18_15 format.
Ic	Machine current for phase C in Fix18_15 format.
gates	Concatenated IGBT gate signals in (6-bit format). The MSB bit corresponds to phase A top IGBT, while the MSB-1 bit corresponds to phase A bottom IGBT. Phase B and C are controlled similarly (down to the LSB controlling the phase C bottom IGBT).
Vbemf_A	Back-EMF induced voltage for phase A in F18_15 format.
Vbemf_B	Back-EMF induced voltage for phase B in F18_15 format.
Vbemf_C	Back-EMF induced voltage for phase C in F18_15 format.
noIGBTpulse	This 1-bit signal disables all IGBT pulses.
model_sync	CPU synchronization signal. Used to sum up the DC-link current.

Outputs

Va	Phase A inverter voltage, in Fix18_15 format.
Vb	Phase B inverter voltage, in Fix18_15 format.
Vc	Phase C inverter voltage, in Fix18_15 format.
Rmach	High impedance phase signal (UFix3_0) to be connected to the phase domain machine model.

Characteristics and Limitations

This block requires a specific license for FPGA configuration file generation and during runtime.

Direct Feedthrough	N/A
Discrete sample time	N/A
XHP support	N/A
Work offline	NO

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