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Description

The FPGA Synthesis Manager is a convenient utility to manage model translation into FPGA interpretable VHDL code and to integrates this model into the framework of the OPAL-RT communication and I/O interfaces. It enables the user to generate a programming file for the reconfigurable chip of various boards. It also enables the automatic Programming of the board using a JTAG connection.

The block also allows a user to set the version of the bitstream that will be generated when the XSG model is compiled (Version configuration button).

The Hardware configuration button is provided to help the user find the appropriate analog or digital, input or output signal interface on the OPAL-RT real-time simulator system (See the help of the block once click on the button for more details).

Parameters

• Hardware configuration: Use this button to open the Hardware Configuration panel and select the exact configuration and location for each I/O module present on the target system.
• Version configuration: Use this button to open the Version Configuration panel. It allows setting the bitstream version as well as some advanced options.
• FPGA development board: This parameter presents the list of the supported boards for generating the bitstream.
• Clock Frequency: Depending on the FPGA selected, it may be possible to select between 100MHz or 200MHz.

• Oversampling Clock Frequency: This parameter specifies the clock frequency used as the based clock for the Digital input Oversampling feature. The Digital inputs will be sampled 4 times per Oversampling clock cycle (so effectively at 4 times the oversampling frequency). By default, 400Mhz is used for the eHS Gen5 block on Kintex-7 and Virtex-7 FPGA, 500Mhz is used on Versal FPGA.
  • A clock will be generated at the frequency specified by this option, and could be used to clock Asynchronous blackbox design. To use the generated clock, use a block FROM with the global tag "OversamplingClock_0".
• Implementation Strategy: This parameter gives to the user new strategies in addition to the default one. It is hardly recommended to keep the default one unless the timing closure is not reached with it. In other words, if the user encounters some timing errors, he can proceed to a new iteration of generating a bitstream by using another implementation strategy that is more suitable to its design. Using directly other strategy than the default one right at the first iteration of generating a bitstream without knowing that its timing closure can be reached, is not recommended.
  
  • This parameter presents the list of the available implementation strategies to be use during the bitstream generation process. Refer to Xilinx's UG904 documentation and UG835 for information on the syntax and effect of each strategies to help choosing one of the available strategies.
    
    • Selecting "User defined" and going through the configuration will end-up saving the established strategy under a folder within the RT-XSG's installation path. Primary folder will be named "AppData_RTXSG" and the secondary folder will have the name given to the strategy. The strategy can then be shared and reused and could be deterministic (depends on Xilinx tool revision).

• Architecture Type: This parameter presents a list of High-Speed Link (MuSE) application architecture choices. Selecting option Central/Standard implements a typical central High-Speed Communication architecture in the FPGA. Selecting option Remote implements a typical remote High-Speed Communication architecture in the FPGA. Selecting option No MuSE implements a standard architecture in the FPGA without High Speed Communication.

List of module compatibilities for the MuSE feature

• MuSE Line Rate: This option is reserved for future use. The default value for the line rate is currently 5 Gbps.
• Enable IP Cache: When this option is checked, System Generator incorporates a disk cache to speed up the iterative design process (When new customization of the IP is created which has the exact same properties, the IP is not synthesized again, instead, the cache is referenced and the corresponding synthesis output in the cache is copied to your design's output directory).
  • The full path to the IP cache directory will display in the MATLAB command window with this command: xilinx.environment.getipcachepath
• Generate file: Use this button to generate the file previously selected with the checkboxes 'Bitstream file' and/or 'Configuration file' explain after.

• OPBIN (OPAL-RT Bitstream File): This file format contains the FPGA's Bitstream and Configuration file as well as additional information on the features present in the firmware that can be used by components of the RT-LAB or HYPERSIM suites for configuration.
  It is the recommended format if you intend to use a bitstream with RT-LAB or HYPSERSIM suite from version onwards 2020.1.

• Bitstream file: This option allows the generation of the file that will be used to program the FPGA board.
  It is the recommended format if you intend to use the generated bitstream with RT-LAB or HYPSERSIM suite earlier than version 2020.1.
• Configuration file: This option allows the generation of the configuration file which represents the I/O described by the model.
  It is the recommended format if you intend to use the generated bitstream with RT-LAB or HYPSERSIM suite earlier than version 2020.1.

Inputs

None.

Outputs

None.

Characteristics and Limitations