Block

Block

Description

This block is used to implement the point-to-point communication link between a pair of field programmable logic arrays (FPGAs) in the simulation system. This communication uses the 5 Gbps, 8b/10b Aurora protocol.

This block must be used in an RT-XSG model with a properly configured InterFPGA_SyncPeriod block. When using this block, some extra care is required from the user to properly set the mask parameters to what is expected and required by the model.

It is necessary to know in advance how much data are to be sent on how much ports so a proper FPGA sync period can be set in the InterFPGA_SyncPeriod block. The following graph can help the user determine the right sync period to use depending on how much data on how many ports are required.

The graph gives the following information:

Each line describes the time to complete transmission of a given quantity of data per ports, with identification of the lines as per the legend to the right of the graph.
The lines equations are given only as a general guideline based on several tests made with the InterFPGA comm block and should only be used for extrapolation on this graph. They shall not be used as precise evidences of the block's performances.
There is an initial overhead for the transmission of data, which is found to be around 0,40 us on the OP5607 and 0,50 us on OP4500. In any case the FPGA sync period cannot be lower than these values.
To the initial overhead, one needs to add a transmission time per data sent. This transmission time per data corresponds to the slope of the lines on the graph.

The graph can be used in the following way to determine the FPGA sync period:

First, determine how many ports you will use and how much data will go through each port.
Try to even the quantity of data per port as this block works best when transmitting data in parallel (i.e. 1 data per port times 32 ports will be faster than 32 data on a single port).
If the quantity of data is not even between the ports, assume all ports transmit the same, highest quantity of data.
Set the buffer depth for the transmission (FPGA_OUT (TX)) to the expected quantity of data to transmit per port.
Set the buffer depth for the reception (FPGA_IN (RX)) to the expected quantity of data to receive per port. This value can be different than on the TX side. The important thing is to match what is specified in the InterFPGA comm block used on the other FPGA.
Look on the graph for the line with the number of ports you use. If no lines correspond to your number of ports, visual interpolation should be used. Find the intersection corresponding to your quantity of data per port, giving you the expected time to complete the transmission.
In the InterFPGA_SyncPeriod, the sync period should be at the very least this transmission value, but we suggest to make it 20 % more to make sure the InterFPGA comm has enough time to complete transmission. Also make sure that the model's time step is a multiple of the FPGA sync period. For example, if Ts = 20 us, FPGA sync period can be 1, 2, 4, etc. up to 20 us, but not 8 or 12.

Parameters

Configuration Tab

Configuration tab

Channel Number Selection	Sets current Channel number used in the communication link between a pair of field programmable logic array (FPGA).
MGT Reference Clock Selection	Sets the reference clock speed of the Multi-gigabit Transceivers used in the communication Channel. It is fixed to 125 MHz and is not editable. A future enhancement will allow selectable Reference Clock.
Line Rate Selection	Sets the Channel Line Rate. It is fixed to 5 Gbps and is not editable. A future enhancement will allow selectable line rate.
Protocol Selection	Sets the communication protocol. It is fixed to Aurora 8B/10B and is not editable.
Sample Period	Sets the FPGA clock period. It is fixed to the RT-XSG model clock period and is not editable.
Provide status ports	When this parameter is set, the Aurora protocol debug signals are made available in the output of the block. These parameters are intended for debugging purpose only, and their use is recommended for advanced users only. The available debugging ports are: rx_overrun_error: Reception buffer did not have time to get empty before the occurrence of the current Inter-FPGA communication synchronization period. This can happen if the Inter-FPGA communication synchronization period is too short. rx_overflow_error: Reception buffer was not able to accommodate all incoming data. In normal operation, this eventuality is never encountered. tx_overrun_error: Transmission buffer did not have time to get empty before the occurrence of the current Inter-FPGA communication synchronization period. This can happen if the Inter-FPGA communication synchronization period is too short. tx_overflow_error: Transmission buffer was not able to accommodate all incoming data. This can happen if the model sends more data than the buffer size during one the inter-FPGA communication synchronization period. HARD_ERROR: Communication hardware error. SOFT_ERROR: Communication software error. LANE_UP: Communication lane-up signal. This signal gets active once the Aurora-protocol based inter-FPGA point-to-point communication channel is properly set up. CHANNEL_UP: Communication channel-up signal. This signal gets active once the Aurora-protocol based inter-FPGA point-to-point communication channel is properly set up.

FPGA_IN (RX) Tab

FPGA_IN (RX) tab

Number of channels	Sets the number of communication ports to be implemented in the reception side of this interface. It must match the corresponding parameters in the FPGA_OUT (TX) tab of remote FPGA. interface configuration block.
Maximum number of channels	Gives the maximum number of channels available in the reception side of this interface. It is not editable.
Buffering type, from the highest numbered port down to FpgaIN1	Sets the buffering type of each communication port. It should be a vector of zeros and ones. Zeros stand to a register buffer type (only one data per communication synchronization period - NOT IMPLEMENTED YET). Ones stand for First-In-First-Out buffer type, enabling the reception of zero, one or more data per communication synchronization period. It must match the corresponding parameter in the FPGA_OUT (TX) tab of the remote FPGA interface configuration block.
FIFO common depth	Sets the depth of the First-In-First-Out-buffer-type port, i.e. the maximum number of data words that can be received during each communication synchronization period. It must match the transmission buffer depth in the FPGA_OUT (TX) tab of the remote FPGA interface configuration block.
Transfer Mode, from the highest numbered port down to FpgaIN1	Sets the data reception pattern. It should be a vector of zeros (standing for "Synchronous" - NOT IMPLEMENTED YET) and ones (standing for "Asynchronous"). "Synchronous" means that all data will be made available, sequentially and contiguously, following the communication synchronization pulse marking the end of the synchronization period they were received into. "Asynchronous" means that any received data work will be made available as it arrives in the interface. See the "Characteristics and limitations" section for more details on transmission timing.
Provide Start and End of Frame	When set, start and end of frame output ports will be made available on the block reception side. It should match the corresponding parameter in the FPGA_OUT (TX) tab of the remote FPGA interface configuration block.
Number of ports with Start and End of Frame	Sets the number of ports for which the start and end of frame feature is implemented. It is available only if the start and end of frame feature are selected, and ranges from 1 port to 4 ports. It must match the corresponding parameter in the remote FPGA interface configuration block.
Place Start and End of Frame ports on the upper FpgaIN ports	If set, the selected number of start and end of frame ports are attached to the highest output ports of the block (FpgaIN1, FpgaIN2, etc.). Otherwise, they are attached to the lowest ports. It must match the corresponding parameter in the FPGA_OUT (TX) tab of the remote FPGA interface configuration block.

FPGA_OUT (TX) Tab

FPGA_OUT (TX) tab

Number of channels	Sets the number of communication ports to be implemented in the transmission side of this interface. It must match the corresponding parameters in the FPGA_IN (RX) tab of remote FPGA interface configuration block.
Maximum number of channels	Gives the maximum number of channels available in the transmission side of this interface. It is not editable.
Buffering type, from the highest numbered port down to FpgaOUT1	Sets the buffering type of each communication port. It should be a vector of zeros and ones. Zeros stand to a register buffer type (only one data per communication synchronization period - NOT IMPLEMENTED YET). Ones stand for First-In-First-Out buffer type, enabling the transmission of zero, one or more data per communication synchronization period. It must match the corresponding parameter in the FPGA_IN (RX) tab of the remote FPGA interface configuration block.
FIFO common depth	Sets the depth of the First-In-First-Out-buffer-type port, i.e. the maximum number of data words that can be transmitted during each communication synchronization period. It must match the reception buffer depth in the FPGA_IN (RX) tab of the remote FPGA interface configuration block.
Provide Start and End of Frame	When set, start and end of frame input ports will be made available on the block transmission side. It should match the corresponding parameter in the FPGA_IN (RX) tab of the remote FPGA interface configuration block.
Number of ports with Start and End of Frame	Sets the number of ports for which the start and end of frame feature is implemented. It is available only if the start and end of frame feature is selected, and ranges from 1 port to 4 ports. It must match the corresponding parameter in the remote FPGA interface configuration block.
Place Start and End of Frame ports on the upper FpgaOUT ports	If set, the selected number of start and end of frame ports are attached to the highest input ports of the block (FpgaOUT1, FpgaOUT2, etc.). Otherwise, they are attached to the lowest ports. It must match the corresponding parameter in the FPGA_IN (RX) tab of the remote FPGA interface configuration block.
Provide Transmission Trigger Port (Async TX Mode)	When set, it allows the user to control the moment of the transmission of outgoing data. Otherwise, a periodic signal (FPGASync) is used to trigger the start of data transmission. Usually, when this option is enabled, the user fills up the buffer with data in the amount specified in the field FIFO Common Depth and then triggers the beginning of the transmission. It is mandatory to allow the transaction to complete before starting another one. The transaction time can be estimated using this equation: (Number of User clock cycles to fill the transmitter FIFO * User Clock Period) + Block Latency (560 ns) + { [FPGA_IN FIFO Common Depth * (3 + Number of Channel)] * User Clock Period}

Advanced Tab

Advanced tab

For all of these settings, the optimal value is configured by default.

GTX parameter 'TXDIFFCTRL'	Sets the Driver Swing Control value of the GTX transmitter in order to maximize signal integrity.
GTX parameter 'TXPRECURSOR'	Sets the GTX transmitter pre-cursor TX pre-emphasis.
GTX parameter 'TXPOSTCURSOR'	Sets the GTX transmitter post-cursor TX pre-emphasis.

Inputs

FpgaOUT{1,...,32}	Transmitter communication data ports. Each of those ports is of UFix33_0 format where the first 32 bits represent the data and bit 33 (most significant bit) is the valid signal indicating when the information is updated.

Outputs

FpgaIN{1,...,32}	Receiver communication data ports. Each of those ports is of UFix33_0 format where the first 32 bits represent the data and bit 33 (most significant bit) is the valid signal indicating when the information is valid.

Characteristics and Limitations

This block has no special characteristics.

Direct Feedthrough	NO
Discrete sample time	NO
XHP support	N/A
Work offline	YES

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