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H-Bridge Converter
HSCS SOLVER
This component models an H-bridge topology, obtained by combining two half-bridge legs.
The integration of two half-bridges within the HSCS module enables an optimization that reduces FPGA resource utilization, based on the assumption that a short-circuit condition in one leg is equivalent to a short-circuit in another leg or across all legs simultaneously.
Parameters
Internal on resistance (Ron) | The switch internal on resistance, in ohms (Ω). |
|---|---|
Internal off Resistance (Roff) | The switch internal off resistance, in ohms (Ω). |
Gate control signal (g1) | The signal to control on/off state of the upper switch of the first arm. |
Gate control signal (g2) | The signal to control on/off state of the lower switch of the first arm. |
Gate control signal (g3) | The signal to control on/off state of the upper switch of the second arm. |
Gate control signal (g4) | The signal to control on/off state of the lower switch of the second arm. |
Electrical Ports
From top to bottom, the electrical ports are the positive, the first AC, the second AC, and negative ports.
Inputs
g1 | Digital input controlling the gate of the upper switch of the first arm. This input could be assigned to a digital input channel or a signal coming from Simulink or HYPERSIM. |
|---|---|
g2 | Digital input controlling the gate of the lower switch of the first arm. This input could be assigned to a digital input channel or a signal coming from Simulink or HYPERSIM. |
g3 | Digital input controlling the gate of the upper switch of the second arm. This input could be assigned to a digital input channel or a signal coming from Simulink or HYPERSIM. |
g4 | Digital input controlling the gate of the lower switch of the second arm. This input could be assigned to a digital input channel or a signal coming from Simulink or HYPERSIM. |