eHS Build Report

Once an FPGA circuit model has been processed by the eHS Solver, an eHS Build Report is generated containing detailed information about the processed model and the selected solver configuration. The report can be used to troubleshooting issues, verify solver settings, analyze FPGA resource usage, and optimize the circuit topology or solver parameters.

Refer to the documentation for your simulation platform for instructions on generating and accessing the Build Report.

Report Contents

A sample eHS Build Report is shown below. The report begins with a header indicating the date and time at which the circuit model was processed by the eHS Solver.

=== Circuit built on 2026-06-22 01:38:49 ===

=== General ===

    EFPGASIM : Core_v3.5.4
    Unified Database : 4.8.0
    Schematic Editor : v3.7.0
    Output Path : C:\Users\eFPGASIM_Automation2\OPAL-RT\RT-LABv2026.2_Workspace\Bandwidth\models\test\EFPGASIMConfig\logs\RCLowPass1Meas1Ckt
    Setup name : Setup 1
    Bitstream File : OP5145_2-EX-0001-3_12_5_19-eHSx128Gen5_HSCS_PowerElectronics_IOConfig4-EA-06.pdi
    Circuit : RCLowPass1Meas1Ckt

=== eHS Solver ===

    Solver Generation : eHS Gen 5
    Discretization Method : Backward Euler
    Switch Interpolation : ON
    Effective Timestep (ns) : 160
    Achievable Timestep Range (ns) : 160 - 131070
    Estimated Solver Usage : 4 %
    User Defined eHS Licence Class : x128
    Firmware Core size : x128
    Effective eHS Licence Class : x128
    Solver Strategy : LOWEST_LATENCY
    Number of States : 0 out of 344
    Number of Switches : 0 out of 144
    Number of total solver Sources : 2 out of 128
    Number of total solver High Latency Outputs : 1 out of 128
    Number of Non-Linear/Variable components : 0 out of 64
    Number of total solver Inductance (Series/Parallel/Mutual) : 0
    Number of total solver Capacitance (Series/Parallel) : 0
    Number of total solver Resistance : 0
    Number of Mutual inductance's windings : 0
    Number of Transformers' windings : 0

=== Miscellaneous ===

    Number of SWG Available : 32
    Number of TSDO Channels : 0 out of 64
    Number of AO mapped to measure block : 0
    Number of SFPO mapped to measure block : 0

=== HSCS Solver ===

    Hscs Circuit : hscs1
    Number of occurences : 1
    Discretization Method : BACKWARD_EULER
    Oversampling : OFF
    Effective Timestep (ns) : 32
    Minimum Timestep (ns) : 32
    Firmware Core size : x256Light
    Switches used : 0 % (0 out of 12)
    Input DP capacity used : 12 % (2 out of 16)
    Output DP capacity used : 6 % (1 out of 16)
    External measurements routed : 6 % (1 out of 16)
    Effective oversampling : 32.000 e-9 s

=== IO connections informations ===

    Analog Inputs : 0 out of 16

    Analog Outputs : 1 out of 64
        AO Slot 1 Channel 00
            vmeas1 (V_out)
                Gain : 1.0
                Offset : 0.0
                Min : -Infinity
                Max : Infinity

    Digital Inputs : 0 out of 96

    SFP Inputs : 0 out of 64

    SFP Outputs : 0 out of 64

    Machine encoder outputs A, B and Z connection to digital out
eHS Build Report - Error while generating Digital Out report : Unsupported firmware

=== Details ===

    Sources (Input lane : Name) : 
        - Lane 0 : 
            - 0 : hscs1-vsrc1
        - Lane 3 : 
            - 0 : vsrc1
    Switches Breakdown : 
        
    Thermal Losses gate mapping (Index : Name) : 
    High latency Outputs (Index : Name) : 
        - 0 : vmeas1

The remaining contents of the report are organized into the following sections:

General

The General section summarizes the software versions and configuration information used to generate the processed circuit model.

Parameter	Description

Parameter	Description
EFPGASIM	eFPGASIM version used to process the circuit model.
Unified Database	Unified Database version used during processing.
Schematic Editor	Schematic Editor version used to create the model.
Output Path	Directory containing the Build Report and related log files.
Setup name	Name of the configured Simulator Setup.
Bitstream File	FPGA bitstream file selected for the Simulator Setup.
Circuit	Name of the processed circuit schematic.

=== General ===

    EFPGASIM : Core_v3.5.4
    Unified Database : 4.8.0
    Schematic Editor : v3.7.0
    Output Path : .\RT-LABv2026.2_Workspace\Bandwidth\models\test\EFPGASIMConfig\logs\RCLowPass1Meas1Ckt
    Setup name : Setup 1
    Bitstream File : OP5145_2-EX-0001-3_12_5_19-eHSx128Gen5_HSCS_PowerElectronics_IOConfig4-EA-06.pdi
    Circuit : RCLowPass1Meas1Ckt

eHS Solver

The eHS Solver section summarizes the solver configuration used to process the circuit model, along with the resulting solver capacity and resource utilization.

Parameter	Description

Parameter	Description
Solver Generation	Generation of the eHS Solver used to simulate the circuit model.
Discretization Method	Circuit Discretization Method configured in the schematic Solver Settings.
Switch Interpolation	Switch Interpolation setting defined in the schematic Solver Settings.
Effective Timestep	Time step at which the circuit is simulated on the FPGA.
Achievable Timestep Range	Minimum and maximum time steps supported by the circuit using the current solver configuration. A manual time step within this range can be configured in the schematic Solver Settings.
Estimated Solver Usage	Percentage of available eHS Solver resources consumed by the circuit model.
User Defined eHS License Class	eHS License Class selected by the user in the Simulator Setup.
Firmware Core Size	eHS Solver core size available in the selected FPGA firmware.
Effective eHS License Class	Effective eHS solver core size considering both the selected license class and the limits of the selected FPGA firmware.
Solver Strategy	Solver Strategy configured in the schematic Solver Settings.
Number of Components	Summary of the circuit resource usage reported for each component type, including states, switches, sources, outputs, and passive components.

=== eHS Solver ===

    Solver Generation : eHS Gen 5
    Discretization Method : Backward Euler
    Switch Interpolation : ON
    Effective Timestep (ns) : 160
    Achievable Timestep Range (ns) : 160 - 131070
    Estimated Solver Usage : 4 %
    User Defined eHS Licence Class : x128
    Firmware Core size : x128
    Effective eHS Licence Class : x128
    Solver Strategy : LOWEST_LATENCY
    Number of States : 12 out of 344
    Number of Switches : 5 out of 144
    Number of total solver Sources : 2 out of 128
    Number of total solver High Latency Outputs : 1 out of 128
    Number of Non-Linear/Variable components : 0 out of 64
    Number of total solver Inductance (Series/Parallel/Mutual) : 0
    Number of total solver Capacitance (Series/Parallel) : 0
    Number of total solver Resistance : 0
    Number of Mutual inductance's windings : 0
    Number of Transformers' windings : 0

Miscellaneous

The Miscellaneous section summarizes additional FPGA firmware resources and measurement mappings used by the circuit model.

Parameter	Description

Parameter	Description
Number of SWG Available	Number of Sine Wave Generator resources available in the selected FPGA firmware.
Number of TSDO Channels	Number of Time Stamped Digital Output channels used by the circuit model and available in the selected FPGA firmware.
Number of AO mapped to measure block	Number of Analog Output channels mapped to voltage or current Meter blocks in the circuit schematic.
Number of SFPO mapped to measure block	Number of SFP Output channels mapped to voltage or current Meter blocks in the circuit schematic.

=== Miscellaneous ===

    Number of SWG Available : 32
    Number of TSDO Channels : 0 out of 64
    Number of AO mapped to measure block : 0
    Number of SFPO mapped to measure block : 0

HSCS Solver

The HSCS Solver section summarizes the configuration and resource utilization of each High Speed Converter Solver (HSCS) circuit in the processed circuit model.

Parameter	Description

Parameter	Description
HSCS Circuit	Name of the HSCS circuit. In models containing multiple HSCS instances, this is the name of the primary HSCS block.
Number of Occurrences	Number of instances of the HSCS circuit in the circuit model.
Discretization Method	Discretization Method configured in the HSCS block parameters.
Oversampling	Oversampling setting configured in the HSCS block parameters.
Effective Timestep (ns)	Time step at which the HSCS circuit is simulated on the FPGA.
Minimum Timestep (ns)	Minimum time step supported by the HSCS circuit using the current HSCS and eHS solver configuration.
Firmware Core Size	HSCS core size available in the selected FPGA firmware.
Switches used	Percentage of the available switching component capacity consumed by the HSCS circuit. See Maximum Circuit Size for more information.
Input DP capacity used	Percentage of the available calculation units consumed by states and sources in the HSCS circuit.
Output DP capacity used	Percentage of the available calculation units consumed by states and outputs in the HSCS circuit.
External measurements routed	Percentage of available measurement outputs consumed by the HSCS circuit.
Effective oversampling	Effective execution interval of each interleaved HSCS circuit. For a single HSCS instance, this value is equal to the effective time step.
Decimation factor	Decimation factor applied to HSCS output measurements.

=== HSCS Solver ===

    Hscs Circuit : hscs1
    Number of occurences : 1
    Discretization Method : BACKWARD_EULER
    Oversampling : OFF
    Effective Timestep (ns) : 32
    Minimum Timestep (ns) : 32
    Firmware Core size : x256Light
    Switches used : 0 % (0 out of 12)
    Input DP capacity used : 12 % (2 out of 16)
    Output DP capacity used : 6 % (1 out of 16)
    External measurements routed : 6 % (1 out of 16)
    Effective oversampling : 32.000 e-9 s
    Decimation factor : 1

IO Connection Information

The IO Connection Information section summarizes the allocation of hardware I/O resources used by the circuit model.

Parameter	Description

Parameter	Description
Analog Inputs	Analog Input channels used by the circuit model and the total number available on the selected hardware.
Analog Outputs	Analog Output channels used by the circuit model and the total number available on the selected hardware. For each mapped channel, the associated measurement signal, gain, offset, and output range are listed.
Digital Inputs	Digital Input channels used by the circuit model and the total number available on the selected hardware.
SFP Inputs	SFP Input channels used by the circuit model and the total number available on the selected hardware.
SFP Outputs	SFP Output channels used by the circuit model and the total number available on the selected hardware.
Machine encoder outputs	Mapping of machine encoder output signals (A, B, and Z) to Digital Output channels.

=== IO connections informations ===

    Analog Inputs : 0 out of 16

    Analog Outputs : 1 out of 64
        AO Slot 1 Channel 00
            vmeas1 (V_out)
                Gain : 1.0
                Offset : 0.0
                Min : -Infinity
                Max : Infinity

    Digital Inputs : 0 out of 96

    SFP Inputs : 0 out of 64

    SFP Outputs : 0 out of 64

    Machine encoder outputs A, B and Z connection to digital out

Details

The Details section summarizes the circuit model inputs and outputs from the perspective of the CPU model.

Parameter	Description

Parameter	Description
Sources	Mapping between circuit source components and the eHS Solver input lanes.
Switches Breakdown	Summary of the switching components identified in the compiled circuit.
Thermal Losses gate mapping	Mapping between switch gate indices and the corresponding gate names in the circuit. These indices are used when configuring the Thermal Losses feature for eHS.
High Latency Outputs	Mapping between high-latency output indices and the corresponding measurement signals.

=== Details ===

    Sources (Input lane : Name) : 
        - Lane 0 : 
            - 0 : hscs1-vsrc1
        - Lane 3 : 
            - 0 : vsrc1
    Switches Breakdown : 
        
    Thermal Losses gate mapping (Index : Name) : 
    High latency Outputs (Index : Name) : 
        - 0 : vmeas1