Half Bridge Converter

This block implements a single phase (leg) 2-level half bridge IGBT converter. It enables the LCA feature of eHS Gen4.

A half-bridge converter is a type of DC-DC converter that, like flyback and forward converters, can supply an output voltage either higher or lower than the input voltage and provide electrical isolation via a transformer.

Parameters

Internal on resistance (R_on)	The diode internal on resistance, in ohms (Ω).
Internal off Resistance (R_off)	The diode internal off resistance, in ohms (Ω).
Gate control signal (g₁)	The signal to control on/off state of the first switch.
Gate control signal (g₂)	The signal to control on/off state of the second switch.
Discrete-time switch conductance (G_s)	The discrete-time switch conductance, in S. See How to tune discrete-time switch condutance for detailed explanation.
Prediction (Pred)	The prediction parameter of the switch. Values can range between 0.1 to 10. See How to tune two-level switches for detailed explanation.
Relaxation (Relax)	The relaxation parameter of the switch. Values can range between 0.1 to 10. See How to tune two-level switches for detailed explanation.

Electrical Ports

From top to bottom, the electrical ports are the positive, AC port and negative ports of the source respectively named p1, p2 and n1

Inputs

g1	Digital input controlling the first gate. This input could be assigned to a digital input channel or a signal coming from Simulink or HYPERSIM.
g2	Digital input controlling the second gate. This input could be assigned to a digital input channel or a signal coming from Simulink or HYPERSIM.

Characteristics

Advanced - Gen 4

Advanced parameters for Gen 4 solver architecture:

Discrete-time switch conductance (G_s)

are only visible when selecting Nodal Analysis (Gen4) circuit analysis method in Solver Settings.

Precision on how to tune this parameter can be found here: https://opal-rt.atlassian.net/wiki/spaces/FPET/pages/22924052.

Advanced - Gen 5

Advanced parameters for Gen 5 solver architecture:

Relaxation (Relax)
Damping resistance (R_damp)

are only visible when selecting State-space Analysis (Gen5) circuit analysis method in Solver Settings.

Precision on how to tune those parameters can be found here: https://opal-rt.atlassian.net/wiki/spaces/FPET/pages/250380336.

Schema design limitations

Due to specific 3-lvl topologies internal implementation, it is not possible to combine multiple Half-bridge converters to simulate a 3-lvl component. It will lead to wrong results whatever the chosen solver generation.