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Electrical Characteristics

Neutral Current Limitation

As the OP8110 neutral point for each group is formed by the midpoint of two capacitors across the DC input rails, there are frequency-dependent limits on the maximum current that can flow through the neutral point terminals. This current limitation applies primarily for low-frequencies; above 25Hz the maximum output current of the amplifier (14A_RMS) can flow through the neutral point, while for lower frequencies the maximum neutral current is reduced.

Please note, this low-frequency neutral current limitation is primarily applicable to amplifier configurations that induce large neutral currents, such as single-phase and unbalanced three-phase operation.

The following figure outlines the maximum neutral current (total current of all three neutral terminals within an OP8110 group) vs AC frequency for the OP8110*:

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*NOTE: To attain the maximum neutral current specified in the above graph, the 3 neutral terminals of the respective OP8110 group (located at the rear of the OP8110 unit) should be connected together

Certification

IEC-61010-1 Certification pending

Timing Specifications

The following timing parameters must be considered for the system functionality/stability:

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t_{COM_SET} = Propagation Delay of the set-point: V and/or I, typically around 10ns (negligible)

t_OP8110 = Intrinsic Delay of the OP8110

t_{COM_MES} = Propagation delay of the measurements: V and/or I, typically around 10ns (negligible)

t_RTS = Time required by the real-time simulator to compute and output a set-point

• ≈ 10 to 50µs on CPU (ex: OP4512)

• ≤1µs on FPGA (eFPGASim)

t_d = t_RTS + t_{COM_SET} + t_OP8110 + t_{COM_MES}

Where td is the total time delay of the closed loop, introduced by the power amplifier, measurement, and discrete-time nature of real-time simulator.

The OP8110 provides the following timing characteristics:

Mechanical Dimensions

Environmental Conditions