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 SCHEMATIC EDITOR WORKFLOW

Introduction

This firmware includes:

  • One eHS x128 Gen5 Solver
  • One Analog Output Mapping and Rescaling (AOMR) module
  • One Analog Input Differential Rescaling (AIR) module
  • One Thermal Losses (TL) module
  • One Saturable Transformer (satXFO) module


LoadIn/DataIn/DataOut mapping


LoadIn

DataIn

DataOut

1

Config eHS

Inputs eHS

eHS Averaged

2

Scenario / Rst eHS = Status

TSDO 1 - eHS 0 to 7

eHS DownSample

3


TSDO 2 - eHS 8 to 15

Digital In 1A - 0 to 7

4

PWM 1A -  0 to 7

TSDO 3 - eHS 16 to 23

Digital In 1A - 8 to 15

5

PWM 1A -  8 to 15

TSDO 4 - eHS 24 to 31

Digital In 1A - 16 to 23

6

PWM 1A -  16 to 23

TSDO 5 - eHS 32 to 39

Digital In 1A - 24 to 31

7

PWM 1A -  24 to 31

TSDO 6 - eHS 40 to 47

Analog In 2A - 0 to 7

8


TSDO 7 - eHS 48 to 55

Analog In 2A - 8 to 15

9


TSDO 8 - eHS 56 to 63

eHS Period Averaged

10


TSDO 9 - eHS 64 to 71

eHS Period DownSample

11


Digital Out 1A - SDO 0 to 7

TimeOn Averaged

12

Config AOMR

Digital Out 1A - SDO 8 to 15

TimeOn DownSample

13

eHS PWM 1 - eHS 24 to 31

Digital Out 1A - SDO 16 to 23

Thermal Losses

14

eHS PWM 2 - eHS 0 to 7

Digital Out 1A - SDO 24 to 31


15

eHS PWM 3 - eHS 8 to 15



16

eHS PWM 4 - eHS 16 to 23



17

Config eHS AIR



18




19


AOMR/ Analog Out 1B -  0 to 7


20


Analog Out 1B -  8 to 15


21

Config Thermal Losses

Analog Out 2B -  0 to 7


22


Analog Out 2B -  8 to 15


23


eHS PWM 1 -  0 to 7


24


eHS PWM 2 -  8 to 15


25


eHS PWM 3 -  16 to 23


26


eHS PWM 4 -  24 to 31


27


eHS SWG


28




29


30




31


32


33
 Thermal Losses

System Overview


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eHS solver

SPS WORKFLOW SPECIFIC

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Connectivity

SPS WORKFLOW SPECIFIC

Source TypeSource IndexSource NameDetails
Input

0CPU Input
1eHS Analog InSlot 2A - Ch00-15
2Data stream from SFP #00
3Sine Wave Generator
4Saturbale Transformer


Gate0Digital InputSlot 1A - Ch00-31
1PWM
2CPU Gating SignalTSDO 0-32
3CPU Gating SignalTSDO 0-32

SPS WORKFLOW SPECIFIC

To contextualize the Input and Gate Configuration table with this firmware configuration, the eHS firmware config tab must be configured with the following custom input source enumeration:

{'CPU Model',0,128;'Sine Wave Generator',3,32;'Analog In',1,16;'SFP',2,16;'Saturable Transformer',4,32}

And this custom gate sources enumeration:

{'CPU Model',2,32;'Digital Inputs',0,32;'PWM',1,32}

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Communication port configuration for the Thermal Losses (TL) block


Thermal Losses
Data In Port Number33
Load In Port Number21
Data Out Port Number13

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Communication port configuration for the Analog Output Mapping and Rescaling (AOMR) block


AOMR - Slot 1B/2B

VersionV2
Data In Port Number19
Load In Port Number12

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Communication port configuration for the Analog Input Differential Rescaling (AIR) block


AIR - Slot 2A

ChannelsCh00-15
Load In Port Number17

AOMR Output

Lane IndexSignal SourceDetails
0eHS OutputseHS Y01-128
1Data Stream from SFP #01

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Communication port configuration for the Analog Input (AI) block


Slot 2A 

ChannelsCh00-07Ch08-15
Data Out Port Number78

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


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Communication port configuration for the Analog Output (AO) block


Slot 1B

Slot 2B

ChannelsCh00-07Ch08-15Ch00-07Ch08-15
Data In Port Number19202122

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


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Communication port configuration for the Digital Input (DI) block


Slot 1A 

ChannelsCh00-07Ch08-15Ch16-23Ch24-31
Data Out Port Number3456

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


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Communication port configuration for the Digital Output (DO) block


Slot 1A 

ChannelsCh00-07Ch08-15Ch16-23Ch24-31
Data In Port Number11121314
Load In Port Number4567

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment





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