Description

Opal-RT eHS - electric Hardware Solver - is a powerful floating-point solver OPAL-RT is developing that enables the user to simulate an electric circuit on FPGA automatically without having to write the mathematical equations. It merges the simplicity of building electric circuits models with the SimPowerSystem Toolbox with the strength of Opal-RT FPGA-based simulators to solve the currents and voltages within the circuit in real-time with a sample time below 1us.

This block implements a generic eHS solver inside a RT-XSG model describing the firmware of the FPGA board.

Mask Parameters

eHS Solver form factor: This option selects the solver computational unit form factor.

Provide external C input port for control from digital inputs: When this option is selected, an input will be provided for feeding the eHS solver with explicit gating signals originating from digital inputs.

Provide external C input port for control from PWM generators: When this option is selected, an input will be provided for feeding the eHS solver with explicit gating signals originating from RT-XSG-based PWM generators [PWMO blocks].

Provide external U input port for sources from rescaled analog inputs: When this option is selected, an input will be provided for feeding the eHS solver with source inputs signals originating from analog inputs (rescaled by a Analog Input Differential Rescaling Block).

Provide external U input port for sources from another eHS core: When this option is selected, an input will be provided for feeding the eHS solver with source inputs signals originating from another eHS core.

Inputs

eHS param and CPU inputs: This input should be connected to the DataIN and LoadIN blocks through an "eHS Gen3 Unpacking" block. It receives all necessary info from the RT-LAB model.

External C (DIn): If this option is selected in the CPU block, this port enables the use of explicit gating signals coming from digital inputs by eHS. The effective number of bits of this input depends upon the solver form factor. It should be a UFix96_0 signal for a x64 solver or UFix64_0 for a x32 solver.

External C (PWM): If this option is selected in the CPU block, this port enables the use of explicit gating signals generated inside the FPGA by eHS. The effective number of bits of this input depends upon the solver form factor. It should be a UFix72_0 signal for a x64 solver or UFix48_0 for a x32 solver.

External U (AIn - serial): If this option is selected in the CPU block, this port enables the use of rescaled analog inputs as sources by eHS. It should be connected to the serial output of an Analog Input Differential Rescaling Block.

External U (other eHS): If this option is selected in the CPU block, this port enables the use of an output originating from another eHS core to control a current or voltage source in the solver. It should be connected to the "eHS Outputs" output of an eHS Gen3 Block.

Outputs

To CPU: This output contains packaged data intended to be connected to the eHS Gen3 Packing block for sending the eHS outputs to the RT-LAB model.

eHS Outputs: This output is a Simulink composite signal containing all eHS outputs for use within the RT-XSG model. It should be connected to a Bus Selector in order to select the appropriate signals from the bus.

Characteristics and limitations

This block has no special characteristics.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.