Description

The 24-Phase Hysteresis Controller block implements the driver of the FPGA-based 24-Phase Hysteresis Controller. The settings of this parameter panel are transformed into the control signals of the FPGA-based controller.

Mask Parameters

IGBT Settings tab

All values in this tab must be positive.

Note: Different snubber resistance and capacitance values can be set independently for Passive and Active mode. Passive mode = none of the igbt of the arm is conducting. Active mode = at least one igbt of the arm is conducting. In this case, the snubber resistance and capacitance must be vectors of 2elements. The first element will be used in passive mode, the second in active mode. This feature could be usefull in case of solver instability when all pulses are off.

Solver Settings tab

Time step: [sec]: Solver time step. It must a value between 300ns and 5us.

Vout/Idc Low pass filter time constant: [sec]: It is possible to setup a low pass filter on the AC voltage and the DC current measurment. This low pass filter could be usefull to insure the solver coupling stability or have a better reading of the waveform (this filter can be seen as an anti-aliasing filter). Note that the Vout low pass filter can modify the overall model behavior since the voltage is used in the motor solver. By default, these filters are disabled (time constant = 0sec).

Configuration tab

Hardware Controller Name (OpCtrl): Controller Name label of the OpCtrl or OpLnk block which must be linked with this block.

FPGA Clock Period: [sec]: This parameter is locked to the FPGA clock period, which is 5ns by default.

Configuration Port Numbers: Port number of the various configuration ports used within by this block. These port numbers are specific to the FPGA firmware version. Please check the bitstream documentation to know these port numbers.

Inputs

Vdc: Input vector of 24 elements used to set the 24 H-briges DC voltage reference. First input corresponds to the first phase Vdc, and so on up to the 24th. If a negative voltage is used, it will make the corresponding Hbridge diodes conduct (then a DC voltage shortcut will happen).

Force_imot: This input can be used to override the current injections. By default the H-bridges current injections comes from the FPGA motor solver. It is still possible to override the currents with force_imot set to 1 and the currents injections values in imot_forced port.

Imot_forced: Values of the override current injections.

Gates_input_sel: The solver takes its gates from the Digital Inputs of the simulator by default. The gate_input_sel port allows the user to use the gates from the internal controller.

If set to 0, the gates are controlled from the simulator digital inputs.
If set to 1, the gates are controlled from the internal controller.
If set to 2, the gates are controlled from the internal test pwm source.
If set to 3, all gates are disabled.

Gates_polarity: The gates polarity can be set with the gates_polarity inport (0 = active high, 1 = active low).

Sh_fault/igbt_open_fault/sw_open_fault: Three fault types are available for all inverter switches: short fault, igbt open fault (diode still working), switch open fault (igbt + diode opened). These 3 ports must be driven by 96 elements vectors. Each element corresponds to a switch (see table below). Setting a 1 will activate the fault on the corresponding switch. Setting a 0 will disable the fault on the corresponding switch.

Vector Element index	1	2	3	4	5	...	96
Switch label	Switch1-phase1	Switch3-phase1	Switch2-phase1	Switch4-phase1	Switch1-phase2	...	Switch4-phase24

Rst: The Rst port is useful in case of solver instability due to wrong block parameters.

Outputs

V_out: the 24 phases voltages of each H-bridge module.

Idc: the 24 phases DC current of each H-bridge module.

comm_status: This output port gives the communication port to/from the FPGA status.

running: The Running port tells if the solver is ready to use or not. When 0, the solver is initialising or in reset mode. When 1 the solver is up and running.

Characteristics and limitations

Models that include this block should be provided with a detailed description document. Refer to this document to obtain more information about the block specifications.

Direct Feedthrough	NO
Discrete sample time	YES
XHP support	YES
Work offline	NO

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.

Block

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