These blocks implement one half of a CPU-FPGA decoupling line.
This model represents a decoupling point on a line by modeling the line parameters and de-coupling latency between CPU and FPGA. The line inductance or capacitance also need to be defined.
Parameters
Symbol | Name | Description | Unit | Type |
|---|---|---|---|---|
Type | Half Line conductance type | Conductance type of the half line. Either inductive or capacitive. | N/A | Input |
Inductance / Capacitance | Half Line conductance value | Conductance value of the half line. Either inductive or capacitive based on selected Type | L / F | Input |
De-coupling latency | CPU / FPGA de-coupling latency | Latency in seconds between FPGA and CPU. When set to “Auto”, eHS will try to determine a valid value based on circuit parameters, The value can be manually edited if the automatic estimate doesn’t match expected results. | s | Input |
How to use
In order to use the de-coupling Half Line with eHS, a half line need to be added in the Schematic Editor electrical model as well as in the CPU model. The parameters of the stubline set in Schematic Editor need to be mirrored manually in the CPU sister block. The CPU sister block outputs SPS power ports to allow coupling between the FPGA based Schematic Editor model and SPS CPU blocks in the Simulink model.
The CPU Half Line block can be found in the eFPGASIM External circuit editor workflow library files.
For each Schematic Editor Half Line, one CPU Half Line should be added to the CPU model. As mentioned earlier, the parameters of the CPU and FPGA (Schematic Editor) half lines should be the same. You can find the values of the parameters of all Schematic Editor Half Lines in the ehsBuildReport log file.
