Block
Mask
Description
The Generic High-Speed Communication Block is a link-layer protocol for high-speed serial communication. The block provides a user interface from which designer can develop a serial link.
The Generic High-Speed Communication Block uses Xilinx's Aurora 8B/10B Core in Framing as a medium for the high-speed communication link.
Parameters
General Settings
| Channel Selection | Selects the current Communication Channel number. |
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| MGT Reference Selection | Selects the reference clock speed of the Multi-Gigabit Transceiver (MGT) of the communication Channel Link. It is forbidden to have different reference clocks in the same MGT Quad.
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| Line Rate Selection | Selects the line rate of the communication channel. It is forbidden to have different line rate in the same MGT Quad.
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| Provide RX FIFO Overflow port | Provides the FIFO overflow status port. |
| Provide Status ports | Provides the Aurora communication core status ports. |
| Provide RX Last Data Port | When checked, an RX Last Data output port is made visible to the user. This port signals the occurrence of the last data of a frame when high. |
| Provide Statistics ports | Provide the Aurora communication core status ports. |
| Provide GT_RESET port | Provide a reset port to reset the internal MGT in the Aurora Core. |
| Ignore CRC Check (RX) | Cyclic Redundancy Check error is ignored/disregarded when this parameter is enabled. |
Advanced Settings
Optimal values are already configured by default.
| MGT 'TXDIFFCTRL' parameter | This parameter sets the Driver Swing Control value of the MGT in order to maximize signal integrity. |
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| MGT 'TXPRECURSOR' parameter | These parameters set the MGT pre-cursor TX pre-emphasis. |
| MGT 'TXPOSTCURSOR' parameter |
Inputs
| TX_DATAVALID | When high indicates that the data present on port TX_DATA is valid when TX_READY is also high. |
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| TX_DATA | Holds a 32-bit outgoing data. |
| TX_LASTDATA | Indicates the last data in the protocol frame. Signals the end of a frame (Active High). |
Optional Ports
This port is available only when Provide GT_RESET Port option is checked.
| GT_RESET | Allows the capability to reset the internal MGT of the Aurora Core. |
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Outputs
| TX_READY | Indicates the communication block is ready to accept incoming data. The block accepts data when both TX_DATAVALID and TX_READY are asserted high. |
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| RX_DATAVALID | Indicates that the data present on port RX_DATA is valid. |
| RX_DATA | Holds the incoming data from the channel partner. |
| FC_CRC_ERROR | Aurora status port indicating a CRC error has been detected. |
Optional Ports
This port is available only when Provide RX FIFO Overflow option is checked.
| FC_FIFO_OVERFLOW_ERROR | Aurora status port indicating the communication interface detects a FIFO Overflow occurrence. |
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These ports are available only when Provide Status Ports option is checked.
| HARD_ERROR | Aurora Status port indicating that the Aurora core has detected a hard error. The core monitors each MGT for hardware errors such as buffer overflow/underflow and loss of lock. |
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| SOFT_ERROR | Aurora Status port indicating a Soft error has been detected in the incoming serial stream. |
| FRAME_ERROR | Aurora Status port indicating a Frame Error. Frames with no data, consecutive Start of Frame symbols, and consecutive End of Frame symbols are considered as Frame Error. |
| LANE_UP | Aurora Status port indicating a successful lane initialization. |
| CHANNEL_UP | Aurora Status port indicating a successful channel initialization and the channel is ready to send/receive data. |
These ports are available only when Provide Statistic Ports option is checked.
| NbrRcvDataPerFrame | Number of data received in a frame. |
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| TimeBetweenFrame | Elapsed time between successive frames. |
| NbrOfFrameError | Number of Frame Error since the start of the simulation. |
| nbrRcvFrame | Number of frame received since the beginning of the simulation. |
Block Handshaking
Transmitting Data
The Generic High SPeed Communication Block is a synchronous interface. The Block samples the data on the interface only on the positive edge of USER_CLK, and only on the cycles when both TX_DATAVALID and TX_READY are asserted (High).
Typical Transaction on the transmit interface:
When the signals are sampled, they are only considered valid if MS_VALID is asserted. The user application can deassert MS_VALID on any clock cycle; this causes the MMC Converter core to ignore the input data for that cycle. If this occurs in the middle of a frame, idle symbols are sent through the Aurora 8B/10B channel, which eventually result in a idle cycles during the frame when it is received at the RX user interface.
Typical Transaction on the transmit interface with throttling
To end the data transfer, the user asserts TX_LASTDATA. The transaction ends when TX_LASTDATA, TX_DATAVALID and TX_READY are all asserted high.
Receiving Data
The Generic High Speed Communication block asserts the signal RX_DATAVALID when the incoming data presents on RX_DATA bus is valid on the user interface. Applications should ignore any values on the receiving ports sampled while the valid flags (RX_DATAVALID) are deasserted (Low).
Note: The Generic High Speed Communication block has a CRC checker mecanism to verify the validity of the data stream. Consequently, there is a latency of 1 frame since the block needs to receive the complete frame and verify the CRC before putting all the data on its output ports.
Characteristics and Limitations
This Block has no specific characteristics or limitations
| Direct Feedthrough | N/A |
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| Discrete sample time | N/A |
| XHP support | N/A |
| Work offline | YES |