Block
Mask
Description
This block is used to set the inter-FPGA communication synchronization period.
Parameters
| Inter FPGA SYnc Period | This parameter sets the inter-FPGA communication synchronization period. The parameter must match the corresponding period in the remote FPGA(s). |
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Inputs
This block has no input.
Outputs
This block has no output.
Characteristics and Limitations
The Inter-FGPA communication period parameter must be large enough to accommodate all data transmitted during the inter-FPGA communication step. If the parameter is set too low, a warning is issued.
IMPORTANT: The CPU model simulation step must be an integer multiple of the inter-FPGA communication synchronization period.
| Direct Feedthrough | NO |
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| Discrete sample time | NO |
| XHP support | N/A |
| Work offline | NO |