Description
The 3-Level-NPC Time Stamped Bridge (TSB) block implements a 3-level Neutral-Clamped bridge with support for high-impedance and free-wheeling diode rectification modes. The bridge models IGBT/GTO/MOSFET devices controlled by ideal switch with their anti-parallel diode. The following figure presents the equivalent electrical circuit of the 3-Level-NPC TSB block with 3 arms.
The working principle of the model is the one of an average model. In the normal continuous conduction mode, the output voltage of each phase is set equal to either V+, Vneutral or V-input voltage multiplied by the conduction time of the gate signal at each time step. In addition to standard TSB models, this model supports the following modes:
| High-Impedance mode | When no pulses are present for the TWO middle IGBT, the output of the model is set in high-impedance mode at the next current zero-crossing. In this mode, the output current goes to 0 after a certain time. |
|---|---|
| Rectifying mode | In this high-impedance mode, if the load voltage becomes higher/lower than the DC-link voltages, the model enters into rectification mode, that is it will simulate the effect of the anti-parallel diodes for rectification. |
Mask and Parameters
| Number of bridge arms | Currently set to 3. |
|---|---|
Active Switch Ron (ohms) Active Switch Forward Voltage (V) Diode Ron (Ohms) Diode Forward Voltage (V) | Internal resistance and forward voltage drop of either IGBT or anti-parallel devices, in Ohms or V. |
High impedance resistance value (Ohms) | This is the value of the output resistance of the inverter output when it enters in the high impedance mode. This value cannot be made arbitrarily high because of numerical stability concerns. |
Use High impedance capacitor | If checked, an RC snubber will be used to emulated the High-impedance mode. |
High impedance capacitor value (F) | When the ’Use high impedance capacitor’ is checked, this is the value of the capacitor of the equivalent RC snubber when the TSB enters in the high impedance mode. |
DC link current Common Mode Removal | The option removes any residual common mode in the DC-link input currents. When the bridge is fed by a floating rectification device for example, this common mode should be non-existent (i.e. the sum of input current should be null). But because the input and output sides of the model are not algebraically linked (they are controlled current and voltage sources), a small residue may be present that may corrupt the simulation accuracy. This option is there to prevent this problem. |
Dead Time current Threshold (A) | This parameter specifies the minimum load current required to turn on anti-parallel diodes when no IGBT pulses are present. |
Inputs and Outputs signals
Gates (double) (size 12) | Signals that controlled the switch gates. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF. A value between 0 and 1 indicates a ratio of conduction time during the time step. |
|---|---|
| V + (SPS) | Positive DC-link SimPowerSystems connection. |
Vn (SPS) | Neutral DC-link SimPowerSystems connection. |
V- (SPS) | Negative DC-link SimPowerSystems connection. |
A,B,C (SPS) | Inverter output connection points (phases A,B and C) for SimPowerSystems |
Vn_delay (SPS) | Neutral connection point for circuits connected to the inverter outputs (ex: LC filter). This connection has a delay equal to the A,B and C connection and this equilibrium of delays is important in some cases. This connection should be used to connect load filter current connection to the Neutral point for example. |
In_meas (size 1) | Measurement of the Neutral Input point. This output is used to measure the real input current of the inverter Vn connection point (current entering point N in the circuit figure). When a circuit is connected to the Vn_delay connection, if a SPS measurement is taken at the Vn input of the inverter, the measured current will include the current flowing through the Vn_delay point, which may not be what is desired. |
Characteristics
| Direct Feedthrough | No |
|---|---|
| Sample Time | Inherited and fixed discrete. |
| Work Offline | Yes |
| Dimensionalized | No |
Limitations
Fault insertion
The 3-Level-NPC TSB Block internal model allows certain faults to be made with it. In all cases, the fault impedance can be limited by numerical stability issues because of the RTE-Drive 3-Level TSB Block introduces a delay between the input and the output of the model.
In particular, the DC voltage should be well-defined for this model to work and consequently, open faults at DC-link should not be done with this model.
Fault type | |
|---|---|
AC-side open phase | Supported. Made internally in SPS. |
AC-side short-circuit | Supported. Made internally in SPS. |
Open DC-link input | Not supported. |
DC-link short circuit | Supported. Made internally in SPS. |
Internal IGBT open-phase fault | Supported through IGBT gating signal. |
Internal IGBT short-circuit | Not supported. |
Diode open-circuit/short-circuit | Not supported. |
Example
The demo model named ThreeLevelInverter_TSB3level_HiZ.mdl shows the proper use of this block.
Related Items
Since ARTEMiS 7.3.2, new TSB models are available in the SSN section of ARTEMiS. These so-called TSB-RD notably have easier and more stable snubber adjustments.